From WikiChip
Editing intel/xeon gold/5218
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 2: | Line 2: | ||
{{chip | {{chip | ||
|name=Xeon Gold 5218 | |name=Xeon Gold 5218 | ||
− | |image= | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5218 | |model number=5218 | ||
− | |||
− | |||
− | |||
− | |||
|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=March, 2019 |
− | |first launched= | + | |first launched=March, 2019 |
− | |||
− | |||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=5000 |
|locked=Yes | |locked=Yes | ||
|frequency=2,300 MHz | |frequency=2,300 MHz | ||
|turbo frequency1=3,900 MHz | |turbo frequency1=3,900 MHz | ||
− | |||
− | |||
− | |||
|clock multiplier=23 | |clock multiplier=23 | ||
− | |cpuid= | + | |cpuid=0x50654 |
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 32: | Line 23: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
− | |||
− | |||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 39: | Line 28: | ||
|core count=16 | |core count=16 | ||
|thread count=32 | |thread count=32 | ||
− | |||
|max cpus=4 | |max cpus=4 | ||
− | + | |tdp=105 W | |
− | |||
− | |||
− | |tdp= | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=81 °C | |tcase max=81 °C | ||
|dts min=0 °C | |dts min=0 °C | ||
|dts max=93 °C | |dts max=93 °C | ||
− | |package | + | |package module 1={{packages/intel/fclga-3647}} |
− | |||
− | |||
}} | }} | ||
− | '''Xeon Gold 5218''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early | + | '''Xeon Gold 5218''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket high performance server microprocessor expected to be introduced by [[Intel]] in early 2019. This chip supports up to 4-way multiprocessing. The Gold 5218, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory. |
− | |||
== Cache == | == Cache == | ||
Line 79: | Line 61: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2400 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=? GiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=107.3 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=17.88 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=35.76 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=71.53 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=107.3 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions |
− | + | | pcie revision = 3.0 | |
− | + | | pcie lanes = 48 | |
− | + | | pcie config = x16 | |
− | |pcie revision=3.0 | + | | pcie config 2 = x8 |
− | |pcie lanes=48 | + | | pcie config 3 = x4 |
− | |pcie config= | ||
− | |pcie config 2=x8 | ||
− | |pcie config 3=x4 | ||
− | |||
}} | }} | ||
Line 135: | Line 113: | ||
|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
− | |||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
Line 151: | Line 128: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
− | |||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
Line 161: | Line 137: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
− | |||
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
|ptt=Yes | |ptt=Yes | ||
− | |||
|mbe=Yes | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
Line 178: | Line 152: | ||
|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
− | |vtd= | + | |vtd=No |
|ept=Yes | |ept=Yes | ||
|mpx=No | |mpx=No | ||
Line 184: | Line 158: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
− | |||
− | |||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 199: | Line 171: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} |
Facts about "Xeon Gold 5218 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5218 - Intel#pcie + |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 23 + |
core count | 16 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | B1 + and B0 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/5218 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables +, Transactional Synchronization Extensions +, Intel VT-d + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
max cpu count | 4 + |
max dts temperature | 93 °C + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 5218 + |
name | Xeon Gold 5218 + |
package | FCLGA-3647 + |
part number | CD8069504193301 + and BX806955218 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) + and $ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) + |
release price (box) | $ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) + |
release price (tray) | $ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) + |
s-spec | SRF8T + |
s-spec (qs) | QRA9 + |
series | 5200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 125 W (125,000 mW, 0.168 hp, 0.125 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |