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{{intel title|Xeon Gold 5215}} | {{intel title|Xeon Gold 5215}} | ||
{{chip | {{chip | ||
+ | |future=Yes | ||
|name=Xeon Gold 5215 | |name=Xeon Gold 5215 | ||
− | |image= | + | |image=skylake sp (basic).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5215 | |model number=5215 | ||
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|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=March, 2019 |
− | |first launched= | + | |first launched=March, 2019 |
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|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=5000 |
|locked=Yes | |locked=Yes | ||
|frequency=2,500 MHz | |frequency=2,500 MHz | ||
|turbo frequency1=3,400 MHz | |turbo frequency1=3,400 MHz | ||
− | + | |clock multiplier=22 | |
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− | |clock multiplier= | ||
|cpuid=0x50655 | |cpuid=0x50655 | ||
|isa=x86-64 | |isa=x86-64 | ||
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|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|core count=10 | |core count=10 | ||
|thread count=20 | |thread count=20 | ||
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|max cpus=4 | |max cpus=4 | ||
− | + | |package module 1={{packages/intel/fclga-3647}} | |
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}} | }} | ||
− | '''Xeon Gold 5215''' is a {{arch|64}} [[deca-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in | + | '''Xeon Gold 5215''' is a {{arch|64}} [[deca-core]] [[x86]] multi-socket high performance server microprocessor set to be introduced by [[Intel]] in late [[2018]]. This chip supports up to 4-way multiprocessing. The Gold 5215, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 3.4 GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory. |
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+ | {{unknown features}} | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2400 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=? GiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=107.3 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=17.88 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=35.76 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=71.53 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=107.3 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions |
− | + | | pcie revision = 3.0 | |
− | + | | pcie lanes = 48 | |
− | + | | pcie config = x16 | |
− | |pcie revision=3.0 | + | | pcie config 2 = x8 |
− | |pcie lanes=48 | + | | pcie config 3 = x4 |
− | |pcie config= | ||
− | |pcie config 2=x8 | ||
− | |pcie config 3=x4 | ||
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}} | }} | ||
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|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
− | |vtd= | + | |vtd=No |
|ept=Yes | |ept=Yes | ||
|mpx=No | |mpx=No | ||
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|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
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}} | }} |
Facts about "Xeon Gold 5215 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5215 - Intel#pcie + |
base frequency | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 25 + |
core count | 10 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | L1 + and L0 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/5215 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables +, Transactional Synchronization Extensions +, Deep Learning Boost + and Intel VT-d + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | 5215 + |
name | Xeon Gold 5215 + |
package | FCLGA-3647 + |
part number | CD8069504214002 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
release price (tray) | $ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) + |
s-spec | SRFBC + |
s-spec (qs) | QRG9 + |
series | 5200 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 20 + |
turbo frequency (1 core) | 3,400 MHz (3.4 GHz, 3,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |