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Latest revision | Your text | ||
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*** Larger [[re-order buffer]] (224 entries, up from 192) | *** Larger [[re-order buffer]] (224 entries, up from 192) | ||
*** Larger scheduler (97 entries, up from 64) | *** Larger scheduler (97 entries, up from 64) | ||
− | **** Larger Integer Register File (180 entries, up from | + | **** Larger Integer Register File (180 entries, up from 160) |
**** Larger Retire (4 µOPs/cycle/thread, up from 4 µOPs/cycle/core)? | **** Larger Retire (4 µOPs/cycle/thread, up from 4 µOPs/cycle/core)? | ||
** Memory Subsystem | ** Memory Subsystem |
Facts about "Skylake (client) - Microarchitectures - Intel"
codename | Skylake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | August 5, 2015 + |
full page name | intel/microarchitectures/skylake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Skylake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |