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{{intel title|Silvermont|arch}} | {{intel title|Silvermont|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
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| name = Silvermont | | name = Silvermont | ||
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| manufacturer = Intel | | manufacturer = Intel | ||
| introduction = 2013 | | introduction = 2013 | ||
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| speculative = Yes | | speculative = Yes | ||
| renaming = Yes | | renaming = Yes | ||
− | |isa= | + | | isa = IA-32 |
− | | | + | | isa 2 = x86-64 |
− | | stages | + | | stages = 14 |
| issues = 2 | | issues = 2 | ||
| inst = Yes | | inst = Yes | ||
| feature = | | feature = | ||
− | | extension = | + | | extension = MMX |
− | | extension 2 = | + | | extension 2 = SSE |
− | | extension 3 = | + | | extension 3 = SSE2 |
− | | extension 4 = | + | | extension 4 = SSE3 |
− | | extension 5 = | + | | extension 5 = SSSE3 |
− | | extension 6 = | + | | extension 6 = SSE4 |
| extension 7 = SSE4.1 | | extension 7 = SSE4.1 | ||
| extension 8 = SSE4.2 | | extension 8 = SSE4.2 | ||
− | | extension 9 = | + | | extension 9 = VT-x |
− | | extension 10 = AES | + | | extension 10 = AES-NI |
− | | extension 11 = | + | | extension 11 = CLMUL |
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| cache = Yes | | cache = Yes | ||
− | | l1i = 32 | + | | l1i = 32 KB |
| l1i per = Core | | l1i per = Core | ||
| l1i desc = 8-way set associative | | l1i desc = 8-way set associative | ||
− | | l1d = 24 | + | | l1d = 24 KB |
| l1d per = Core | | l1d per = Core | ||
| l1d desc = 6-way set associative | | l1d desc = 6-way set associative | ||
− | | l2 = | + | | l2 = 512 |
| l2 per = 2 Cores | | l2 per = 2 Cores | ||
− | | l2 desc = | + | | l2 desc = 8-way set associative |
| core names = Yes | | core names = Yes | ||
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| successor link = intel/microarchitectures/airmont | | successor link = intel/microarchitectures/airmont | ||
}} | }} | ||
− | '''Silvermont''' | + | '''Silvermont''' is [[Intel]]'s [[22 nm]] [[microarchitecture]] for the {{intel|Atom|Atom family}} of [[system on chip]]s. Introduced in 2013, Silvermont was the successor to {{intel|Saltwell}}, targeting smartphones, tablets, embedded devices, and consumer electronics. |
== Codenames == | == Codenames == | ||
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| {{intel|Merrifield}} || {{intel|Tangier}} || Smartphones | | {{intel|Merrifield}} || {{intel|Tangier}} || Smartphones | ||
|- | |- | ||
− | + | | {{intel|Bay Trail}} || {{intel|Valleyview}} || Tablets | |
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− | | {{intel|Bay Trail}} || {{intel| | ||
|- | |- | ||
| {{intel|Edisonville}} || {{intel|Avoton}} || Microservers | | {{intel|Edisonville}} || {{intel|Avoton}} || Microservers | ||
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| {{intel|Edisonville}} || {{intel|Rangeley}} || Embedded Networking | | {{intel|Edisonville}} || {{intel|Rangeley}} || Embedded Networking | ||
|} | |} | ||
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== Architecture== | == Architecture== | ||
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* Support up to {{intel|Westmere}} | * Support up to {{intel|Westmere}} | ||
* Multi-core modular system (up to 8 cores) | * Multi-core modular system (up to 8 cores) | ||
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=== Block Diagram === | === Block Diagram === | ||
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=== Core Modules === | === Core Modules === | ||
[[File:silvermont modules.svg|right|450px]] | [[File:silvermont modules.svg|right|450px]] | ||
− | Silvermont | + | Silvermont employees a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to {{intel|Saltwell|Saltwell's}}: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency. |
==== System Agent ==== | ==== System Agent ==== | ||
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** Hardware prefetchers | ** Hardware prefetchers | ||
** L1 Cache: | ** L1 Cache: | ||
− | *** 32 | + | *** 32 KB 8-way [[set associative]] instruction |
− | *** 24 | + | *** 24 KB 6-way set associative data |
*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** | + | *** 512 KB 8-way set associative |
− | *** | + | *** ECC |
− | *** | + | *** Per core |
** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache | ||
+ | ** Non-Cache Shared State Memory | ||
** RAM | ** RAM | ||
− | *** Maximum of | + | *** Maximum of 1GB, 2 GB, and 4 GB |
*** dual 32-bit channels, 1 or 2 ranks per channel | *** dual 32-bit channels, 1 or 2 ranks per channel | ||
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=== Pipeline === | === Pipeline === | ||
− | While Silvermont share some similarities with {{\\|Saltwell}}, it introduces a number of significant changes that sets it apart from part {{intel|Atom}} microarchitectures. Like {{\\|Saltwell}}, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to | + | While Silvermont share some similarities with {{\\|Saltwell}}, it introduces a number of significant changes that sets it apart from part {{intel|Atom}} microarchitectures. Like {{\\|Saltwell}}, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to [[introduce out-of-order execution]] (OoOE) |
[[File:silvermont pipeline.svg]] | [[File:silvermont pipeline.svg]] | ||
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* {{intel|Avoton}} - SoCs for Microservers | * {{intel|Avoton}} - SoCs for Microservers | ||
* {{intel|Rangeley}} - SoCs for Embedded Networking | * {{intel|Rangeley}} - SoCs for Embedded Networking | ||
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Facts about "Silvermont - Microarchitectures - Intel"
codename | Silvermont + |
core count | 1 +, 2 +, 4 + and 8 + |
designer | Intel + |
first launched | 2013 + |
full page name | intel/microarchitectures/silvermont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Silvermont + |
phase-out | 2015 + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 22 nm (0.022 μm, 2.2e-5 mm) + |