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|l1d desc=12-way set associative | |l1d desc=12-way set associative | ||
|l2=512 KiB | |l2=512 KiB | ||
− | |l2 per= | + | |l2 per=512 KiB |
− | |l2 desc= | + | |l2 desc=12-way set associative |
|l3=2 MiB | |l3=2 MiB | ||
|l3 per=core | |l3 per=core | ||
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|contemporary link=intel/microarchitectures/ice_lake_(server) | |contemporary link=intel/microarchitectures/ice_lake_(server) | ||
}} | }} | ||
− | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream mobile devices. | + | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
For mobile devices, Ice Lake is branded as 10th Generation Core i3, i5, and i7 processors. | For mobile devices, Ice Lake is branded as 10th Generation Core i3, i5, and i7 processors. | ||
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| <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | | <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | ||
|} | |} | ||
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== Process Technology== | == Process Technology== | ||
− | {{ | + | {{see also|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} |
− | + | Ice Lake is fabricated on Intel's second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for {{\\|Cannon Lake}}, 10nm+ features higher performance through higher drive current for the same power envelope. Intel says that Ice Lake is built on their learnings from their Cannon Lake products which were largely treated as a learning vehicle. Between Cannon Lake and Ice Lake, a number of changes were made in order to improve the process for their products. One such change was the addition of an extra metal layer (originally said to be 12, is now presumably 13 on Ice Lake) in order to improve the power delivery of the chip. Additionally, they have improved the threshold voltage of the transistors as well as their MIM cap among other changes. | |
− | + | [[File:intels 10+ and 10++.png|750px]] | |
{{clear}} | {{clear}} | ||
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** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ||
** {{intel|Gen11|l=arch}} GPUs | ** {{intel|Gen11|l=arch}} GPUs | ||
− | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics | + | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT2) (32 Execution Units, 2.67x EUs from {{\\|Gen9}}) |
*** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | *** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | ||
**** 1,024 GFLOPS @ 1 GHz (GT2) | **** 1,024 GFLOPS @ 1 GHz (GT2) | ||
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=== Thunderbolt IO subsystem === | === Thunderbolt IO subsystem === | ||
− | By far the largest new integration in Ice Lake is the Thunderbolt I/O Subsystem. According to Intel, this is the largest integration they have done since the integration of the graphics processing unit in {{\\|Sandy Bridge}}. When Ice Lake was introduced, [[Thunderbolt 3]] was the fastest and most versatile connector that was available. Not only is it four times faster than USB 3.1, but it also supports additional peripherals over [[PCIe]], [[USB 3 | + | By far the largest new integration in Ice Lake is the Thunderbolt I/O Subsystem. According to Intel, this is the largest integration they have done since the integration of the graphics processing unit in {{\\|Sandy Bridge}}. When Ice Lake was introduced, [[Thunderbolt 3]] was the fastest and most versatile connector that was available. Not only is it four times faster than USB 3.1, but it also supports additional peripherals over [[PCIe]], [[USB 3]], and DisplayPort. |
− | Ice Lake contains two modular FIAs, each one connect to a pair of Type-C ports for a total of four ports. The FIA can multiplex between a standard [[USB Type-C connector]] and a [[Thunderbolt connector]]. | + | Ice Lake contains two modular FIAs, each one connect to a pair of Type-C ports for a total of four ports. The FIA can multiplex between a standard [[USB Type-C connector]] and a [[Thunderbolt connector]]. Therefore when not Thunderbolt support is desired, the FIA can serve as a standard USB Type-C connection. Each FIA is connected to the USB controller, Display Engine, and the CIO Router. The CIO Router is the actual Thunderbolt router and it can be thought of as a display engine as well. Ice Lake has a total of four PCIe controllers coming from four root complexes. Two PCIe controllers go to each of the CIOs. Previously, there was just a single PCIe controller going to the Titan Ridge controller, so there was effectively one PCIe controller for both ports. Compared to the prior generation, each port now effectively has double the bandwidth. |
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− | Previously (e.g., with {{\\|Whiskey Lake}}), for OEMs to support Thunderbolt 3 in mobile devices, they had to use Intel's Titan Ridge controller. Titan Ridge was a discrete Thunderbolt 3 chip that came with either one or two dedicated [[Thunderbolt 3]] ports. In order to support everything that was necessary (e.g., legacy [[USB 2]] as well as high speed PCIe Gen 3), the controller was connected to both the CPU and the | + | Previously (e.g., with {{\\|Whiskey Lake}}), for OEMs to support Thunderbolt 3 in mobile devices, they had to use Intel's Titan Ridge controller. Titan Ridge was a discrete Thunderbolt 3 chip that came with either one or two dedicated [[Thunderbolt 3]] ports. In order to support everything that was necessary (e.g., legacy [[USB 2]] as well as high speed PCIe Gen 3), the controller was connected to both the CPU and the hipset. The chipset was connected over four PCIe Gen 3 lanes. The CPU had two DisplayPort connections. Each of those passed over four PCIe Gen 3 lanes. In order to offer legacy I/O support, a direct USB 2.0 link from the PCH went to the port. For charging capabilities, the port was also connected directly to a Power Deliver (PD) controller. In total, 17 PCIe Gen 3 lanes operating at around 8 GT/s were required between the Titan Ridge controller and the chipset and CPU. |
Due to the design complexity introduced by the discrete controller, most mobile devices that made use of Titan Ridge only supported it on one side of the device - typically on the side of the device closer to the controller itself. | Due to the design complexity introduced by the discrete controller, most mobile devices that made use of Titan Ridge only supported it on one side of the device - typically on the side of the device closer to the controller itself. | ||
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− | With Ice Lake, Intel simplified the overall design considerably. The biggest change comes from the fact that most of the Titan Ridge logic has been integrated into the Ice Lake SoC itself, reducing board space, routing, and the overall [[bill of materials]]. Instead of the seventeen lanes that were required by the Titan Ridge controller, Ice Lake exposes just eight lanes – four lanes to each [[retimer]] which drive the signals to the connectors. Therefore, in total there are just eight lanes operating at 20 GT/s instead of seventeen lanes operating at 8 GT/s | + | With Ice Lake, Intel simplified the overall design considerably. The biggest change comes from the fact that most of the Titan Ridge logic has been integrated into the Ice Lake SoC itself, reducing board space, routing, and the overall [[bill of materials]]. Instead of the seventeen PCIe lanes that were required by the Titan Ridge controller, Ice Lake exposes just eight lanes – four lanes to each [[retimer]] which drive the signals to the connectors. Therefore, in total there are just eight lanes operating at 20 GT/s instead of seventeen lanes operating at 8 GT/s. The reduction of lanes, along with their associated components such as the buffers, reduces the overall power consumption of the system. Intel stated that, depending on the exact device design, they saw a reduction of up to 300 mW per port when the port was fully utilized. Previously, the dual-port Titan Ridge controller had a TDP of up to 2.4 W, so the overall saving is fairly sizable. The additional power saving thus translates to better performance as more of the overall power budget can be allocated for the GPU and CPU instead of the I/O. |
One of the other benefits of the Thunderbolt 3 integration is that half of the lanes can be exposed to each side of the device. With the Titan Ridge controller, offering Type-C ports on the side further from the controller was more complex and was quite rare and most OEMs simply opted to offer a legacy connector of some sort such as a USB 2.0 on that side. With Ice Lake, the direct Thunderbolt lanes that go to each retimer are easily exposed to both sides of the device, meaning, at least in theory, OEMs should have no problem offering symmetrical connections on both sides of the device. | One of the other benefits of the Thunderbolt 3 integration is that half of the lanes can be exposed to each side of the device. With the Titan Ridge controller, offering Type-C ports on the side further from the controller was more complex and was quite rare and most OEMs simply opted to offer a legacy connector of some sort such as a USB 2.0 on that side. With Ice Lake, the direct Thunderbolt lanes that go to each retimer are easily exposed to both sides of the device, meaning, at least in theory, OEMs should have no problem offering symmetrical connections on both sides of the device. | ||
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− | {{center|''' | + | {{center|'''Thunderbolt 3 support on Ice Lake through the Thunderbolt 3 integration<br>Full configuration with four ports and every feature through every port'''}} |
== Clock domains == | == Clock domains == |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | May 27, 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |