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|introduction=May 27, 2019 | |introduction=May 27, 2019 | ||
|process=10 nm | |process=10 nm | ||
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|l1i per=core | |l1i per=core | ||
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|l1d per=core | |l1d per=core | ||
|l1d desc=12-way set associative | |l1d desc=12-way set associative | ||
+ | |l1 per=core | ||
|l2=512 KiB | |l2=512 KiB | ||
− | |l2 per= | + | |l2 per=512 KiB |
− | |l2 desc= | + | |l2 desc=12-way set associative |
|l3=2 MiB | |l3=2 MiB | ||
|l3 per=core | |l3 per=core | ||
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|contemporary link=intel/microarchitectures/ice_lake_(server) | |contemporary link=intel/microarchitectures/ice_lake_(server) | ||
}} | }} | ||
− | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream | + | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
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== Codenames == | == Codenames == | ||
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| <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | | <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | ||
|} | |} | ||
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== Process Technology== | == Process Technology== | ||
− | {{ | + | {{see also|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} |
− | + | Ice Lake is fabricated on Intel's second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for {{\\|Cannon Lake}}, 10nm+ features higher performance through higher drive current for the same power envelope. Intel says that Ice Lake is built on their learnings from their Cannon Lake products which were largely treated as a learning vehicle. Between Cannon Lake and Ice Lake, a number of changes were made in order to improve the process for their products. One such change was the addition of an extra metal layer (originally said to be 12, is now presumably 13 on Ice Lake) in order to improve the power delivery of the chip. Additionally, they have improved the threshold voltage of the transistors as well as their MIM cap among other changes. | |
− | + | [[File:intels 10+ and 10++.png|750px]] | |
{{clear}} | {{clear}} | ||
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** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ||
** {{intel|Gen11|l=arch}} GPUs | ** {{intel|Gen11|l=arch}} GPUs | ||
− | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics | + | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics 7xx (GT2) (32 Execution Units, 2.67x EUs from {{\\|Gen9}}) |
*** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | *** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | ||
**** 1,024 GFLOPS @ 1 GHz (GT2) | **** 1,024 GFLOPS @ 1 GHz (GT2) | ||
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The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC that is aimed at the mainstream to premium mobile and the thin-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance. | The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC that is aimed at the mainstream to premium mobile and the thin-and-light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance. | ||
− | The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). | + | The system architecture in Ice Lake has been redesigned. Intel added a new Gaussian Neural Accelerator (GNA) for the acceleration of inference applications. There is a new 4th-generation [[image processing unit]] (IPU). There is a new Thunderbolt 3 integration. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression. |
Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | ||
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== Integration == | == Integration == | ||
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=== GNA === | === GNA === | ||
Ice Lake introduced a new low-power [[neural processor]] called the '''Gaussian Neural Accelerator v1.0''' ('''GNA''') which is integrated on the SoC and runs at very low power even when the GPU and CPUs are turned off. The GNA can be used for long-running tasks (e.g., real-time meeting transcription). The GNA can operate while the remaining parts of the SoC are in idle in order to have minimal impact on performance. | Ice Lake introduced a new low-power [[neural processor]] called the '''Gaussian Neural Accelerator v1.0''' ('''GNA''') which is integrated on the SoC and runs at very low power even when the GPU and CPUs are turned off. The GNA can be used for long-running tasks (e.g., real-time meeting transcription). The GNA can operate while the remaining parts of the SoC are in idle in order to have minimal impact on performance. | ||
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=== IPU === | === IPU === | ||
Ice Lake incorporates 4th generation [[image processing unit]] (IPU). The IPU was first introduced with {{\\|Skylake (client)|Skylake}} mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements. | Ice Lake incorporates 4th generation [[image processing unit]] (IPU). The IPU was first introduced with {{\\|Skylake (client)|Skylake}} mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements. | ||
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== Clock domains == | == Clock domains == | ||
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[[File:ice lake soc clock domain block diagram.svg|850px]] | [[File:ice lake soc clock domain block diagram.svg|850px]] | ||
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== Packaging == | == Packaging == | ||
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=== Thin-film magnetic inductor === | === Thin-film magnetic inductor === | ||
− | + | Interestingly the new packages include a thin-film magnetic inductor array on the landing side. Those are said to have higher efficiency at lower power but also support the fully processor dynamic frequency range. They can be distinctly seen on the back of the chip. | |
== Die == | == Die == |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | May 27, 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |