From WikiChip
Editing intel/microarchitectures/ice lake (client)
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 7: | Line 7: | ||
|introduction=May 27, 2019 | |introduction=May 27, 2019 | ||
|process=10 nm | |process=10 nm | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|isa=x86-64 | |isa=x86-64 | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
Line 54: | Line 14: | ||
|l1d per=core | |l1d per=core | ||
|l1d desc=12-way set associative | |l1d desc=12-way set associative | ||
+ | |l1 per=core | ||
|l2=512 KiB | |l2=512 KiB | ||
− | |l2 per= | + | |l2 per=512 KiB |
− | |l2 desc= | + | |l2 desc=12-way set associative |
|l3=2 MiB | |l3=2 MiB | ||
|l3 per=core | |l3 per=core | ||
Line 69: | Line 30: | ||
|contemporary link=intel/microarchitectures/ice_lake_(server) | |contemporary link=intel/microarchitectures/ice_lake_(server) | ||
}} | }} | ||
− | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream | + | '''Ice Lake''' ('''ICL''') '''Client Configuration''' is [[Intel]]'s successor to {{\\|Cannon Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
− | |||
− | |||
== Codenames == | == Codenames == | ||
Line 86: | Line 45: | ||
| <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | | <s>{{intel|Ice Lake S|l=core}}</s>? || <s>ICL-S</s> || <s>Performance-optimized lifestyle</s> || || <s>Desktop performance to value, AiOs, and minis</s> | ||
|} | |} | ||
− | |||
− | |||
− | |||
== Process Technology== | == Process Technology== | ||
− | {{ | + | {{see also|intel/microarchitectures/cannon lake#Process_Technology|l1=Cannon Lake § Process Technology}} |
− | + | Ice Lake will use a second-generation enhanced [[10 nm process]] called "10 nm+". Versus the first generation 10nm which was used for Cannon Lake, 10nm+ will feature higher performance through higher drive current for the same power envelope. | |
− | + | [[File:intels 10+ and 10++.png|750px]] | |
{{clear}} | {{clear}} | ||
Line 141: | Line 97: | ||
** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ** {{intel|Gen10|l=arch}} → {{intel|Gen11|l=arch}} graphics (''Gen10 was never productized'') | ||
** {{intel|Gen11|l=arch}} GPUs | ** {{intel|Gen11|l=arch}} GPUs | ||
− | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics 9xx (GT2) ( | + | *** UHD Graphics 6xx (GT1) '''→''' UHD Graphics 9xx (GT2) (24 Execution Units, 2x EUs from {{\\|Gen9}}) |
*** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | *** UHD Graphics 6xx (GT2) '''→''' Iris Plus Graphics 9xx (GT2) (48-64 Execution Units, 2-2.6x EUs from {{\\|Gen9}}) | ||
**** 1,024 GFLOPS @ 1 GHz (GT2) | **** 1,024 GFLOPS @ 1 GHz (GT2) | ||
Line 147: | Line 103: | ||
** Gen 11.5 (from Gen9/Gen9.5) | ** Gen 11.5 (from Gen9/Gen9.5) | ||
** DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2) | ** DisplayPort 1.4a with Display Stream Compression(DSC) (from DisplayPort 1.2) | ||
− | ** | + | ** HDMI 2.0 (from HDMI 1.4) |
* IPU | * IPU | ||
** 4th Gen IPU (from 3rd Gen in {{\\|Skylake (client)|Skylake}}) | ** 4th Gen IPU (from 3rd Gen in {{\\|Skylake (client)|Skylake}}) | ||
Line 153: | Line 109: | ||
** New concurrent image pipeline | ** New concurrent image pipeline | ||
** on-die MIPI interface | ** on-die MIPI interface | ||
− | |||
− | |||
* I/O | * I/O | ||
** Thunderbolt 3 over Type-C | ** Thunderbolt 3 over Type-C | ||
− | |||
− | |||
− | |||
− | |||
{{expand list}} | {{expand list}} | ||
====New instructions ==== | ====New instructions ==== | ||
− | + | Ice Lake introduced a number of {{x86|extensions|new instructions}}. See {{intel|Sunny cove#New instructions|Sunny Cove § New Instructions|l=arch}} for details. | |
− | Ice Lake introduced a number of {{x86|extensions|new instructions}}. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Block Diagram === | === Block Diagram === | ||
Line 203: | Line 130: | ||
== Overview == | == Overview == | ||
[[File:ice lake overview.svg|right|500px]] | [[File:ice lake overview.svg|right|500px]] | ||
− | The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC | + | The Ice Lake [[system on a chip]] is a [[10-nanometer]] SoC aimed at mainstream to premiume mobile and thin & light market. The microprocessor consists of five major components: CPU cores, LLC, {{intel|ring interconnect}}, {{intel|system agent}}, and {{\\|Gen11}} graphics. While a lot of what Ice Lake provides is inherited from the prior generations, Intel claims that every IP on Ice Lake has been enhanced in one way or another. A major enhancement in Ice Lake over the prior generation is the integration of up to four {{\\|Sunny Cove}} cores which provide a significant uplift in IPC. Those cores also bring {{x86|AVX-512}} support for the client market. Those cores, along with the system agent and the GPU, are linked over Intel's {{intel|ring interconnect}}. The chip is fed through a new [[integrated memory controller]] that supports quad-channel 32-bit LPDDR4X memory, providing bandwidths in the range of 50-60 GB/s. Ice Lake has a new integrated GPU which is based on their {{\\|Gen11}} microarchitecture which provides a large improvement in graphics performance. |
− | The system architecture in Ice Lake has been redesigned | + | The system architecture in Ice Lake has been redesigned. There is a new 4th-generation [[image processing unit]] (IPU). There is a new Thunderbolt 3 integration. Ice Lake has four Thunderbolt 3 ports. All four ports have the same capabilities and can be used simultaneously at full performance at up to 40 Gbps per port. Intel also upgraded the display engine to {{\\|Gen11}} with an improved display pipe that has a new Adaptive Sync and HDR-capable display pipes that support HDR 3 and DisplayPort 1.4, supporting error correction and compression. |
Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | ||
Line 214: | Line 141: | ||
{{empty section}} | {{empty section}} | ||
− | + | == IPU == | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
Ice Lake incorporates 4th generation [[image processing unit]] (IPU). The IPU was first introduced with {{\\|Skylake (client)|Skylake}} mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements. | Ice Lake incorporates 4th generation [[image processing unit]] (IPU). The IPU was first introduced with {{\\|Skylake (client)|Skylake}} mobile SoCs (note that those were 3rd gen). The 4th Gen IPU found in Ice Lake introduces a number of new enhancements. It introduces new support for 4K video capture at 30fps. There is also new hardware support for better de-noising which supports up to 16 megapixels stills in low light conditions. In addition for support more camera simultaneously, the IPU incorporates a new concurrent image pipeline, supporting multiple different processing from the same camera stream, allowing a single camera to take the functionality of multiple sensors. A common example of that is devices with both IR and RGB cameras in the laptop bezel which can now be changed to a single camera. Intel says they are exposing more registers from the IPU to software in order to provide more flexibility for applications that make use of that for machine learning. It’s also worth noting that Intel integrated the MIPI interface onto the processor as well. Previously that was found on the chipset. The change significantly improves the latency, a required attribute needed for more advanced ML-specific applications. Some of those changes are designed to form the foundation for future generations of improvements. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Clock domains == | == Clock domains == | ||
Line 280: | Line 155: | ||
[[File:ice lake soc clock domain block diagram.svg|850px]] | [[File:ice lake soc clock domain block diagram.svg|850px]] | ||
− | |||
− | |||
− | |||
− | |||
− | |||
== Packaging == | == Packaging == | ||
Line 302: | Line 172: | ||
|- | |- | ||
| Ball Pitch || 0.65 mm || 0.43 mm | | Ball Pitch || 0.65 mm || 0.43 mm | ||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
− | |||
− | |||
− | |||
== Die == | == Die == | ||
Line 316: | Line 179: | ||
** 4th Gen IPU | ** 4th Gen IPU | ||
** Gen11 Display | ** Gen11 Display | ||
− | ** Thunderbolt 3 over Type-C | + | ** Thunderbolt 3 over Type-C |
+ | ** PCIe | ||
Line 323: | Line 187: | ||
:[[File:ice lake die sa (annotated).png|700px]] | :[[File:ice lake die sa (annotated).png|700px]] | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Core === | === Core === | ||
Line 351: | Line 197: | ||
:[[File:ice lake die core (annotated).png|400px]] | :[[File:ice lake die core (annotated).png|400px]] | ||
− | |||
− | |||
− | |||
=== Core group === | === Core group === | ||
Line 365: | Line 208: | ||
:[[File:ice lake die core group (annotated).png|700px]] | :[[File:ice lake die core group (annotated).png|700px]] | ||
− | |||
− | |||
− | |||
Line 379: | Line 219: | ||
:[[File:ice lake die gpu (annotated).png|700px]] | :[[File:ice lake die gpu (annotated).png|700px]] | ||
− | |||
− | |||
− | |||
=== SoC === | === SoC === | ||
Line 397: | Line 234: | ||
:[[File:ice lake die (quad core) (annotated).png|700px]] | :[[File:ice lake die (quad core) (annotated).png|700px]] | ||
+ | == All Ice Lake Chips == | ||
+ | {{future information}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
<!-- NOTE: | <!-- NOTE: | ||
This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
Line 417: | Line 245: | ||
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable tc7 tc8 | + | <table class="comptable sortable tc7 tc8 tc20 tc21"> |
− | {{comp table header|main| | + | {{comp table header|main|20:List of Ice Lake-based Processors}} |
− | {{comp table header|main|10:Main processor| | + | {{comp table header|main|10:Main processor|4:{{intel|Turbo Boost}}|Memory|3:GPU|2:Features}} |
− | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|1 Core|2 Cores|4 Cores|Max Memory|Name|Base|Burst}} | + | {{comp table header|cols|Launched|Price|Family|Platform|Core|Cores|Threads|L3$|TDP|Base|1 Core|2 Cores|4 Cores|6 Cores|Max Memory|Name|Base|Burst|{{intel|TBT}}|{{intel|Hyper-Threading|HT}}}} |
− | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake | + | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
Line 437: | Line 265: | ||
|?turbo frequency (2 cores)#GHz | |?turbo frequency (2 cores)#GHz | ||
|?turbo frequency (4 cores)#GHz | |?turbo frequency (4 cores)#GHz | ||
+ | |?turbo frequency (6 cores)#GHz | ||
|?max memory#GiB | |?max memory#GiB | ||
|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
|?integrated gpu max frequency | |?integrated gpu max frequency | ||
+ | |?has intel turbo boost technology 2_0 | ||
+ | |?has simultaneous multithreading | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=21 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[microarchitecture::Ice Lake]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | May 27, 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |