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Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | Ice Lake chips integrate the {{intel|PCH}} die on-package communicating over the on-package interconnect (OPI). The new PCH The PCH has an expanded I/O support for PCIe, USB, SATA, as well as audio DSP for load power voice processing. It also integrates WiFi 6+ {{intel|CNVi}}. | ||
− | On the platform level, there is a new integrated power delivery | + | On the platform level, there is a new integrated power delivery on both the PCH and the CPU which Intel says allows them to save on platform area by about 15% and it reduces the power delivery rails for the OEMs by roughly half. |
== Core == | == Core == |
Facts about "Ice Lake (client) - Microarchitectures - Intel"
codename | Ice Lake (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | May 27, 2019 + |
full page name | intel/microarchitectures/ice lake (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Ice Lake (client) + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |