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Latest revision Your text
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|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
|introduction=November 4, 2021
+
|introduction=2H 2021
 
|process=10nm
 
|process=10nm
 
|isa=x86-64
 
|isa=x86-64
|core name=Alder Lake, Sapphire Rapids
+
|core name=Alder Lake
 
|predecessor=Willow Cove
 
|predecessor=Willow Cove
 
|predecessor link=intel/microarchitectures/willow cove
 
|predecessor link=intel/microarchitectures/willow cove
|predecessor 2=Cypress Cove
 
|predecessor 2 link=intel/microarchitectures/rocket lake
 
 
|successor=Ocean Cove
 
|successor=Ocean Cove
 
|successor link=intel/microarchitectures/ocean cove
 
|successor link=intel/microarchitectures/ocean cove
 
}}
 
}}
'''Golden Cove''' is the successor to {{\\|Willow Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including Sapphire Rapids (server) and Alder Lake (client).  
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'''Golden Cove''' is the successor to {{\\|Willow Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including Granite Rapids(server) and Alder Lake(client).  
  
 
== History ==
 
== History ==
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== Process Technology ==
 
== Process Technology ==
Intel has confirmed that the Golden Cove architecture will be fabricated on their Intel 7 process (previously 10 nm Enhanced SuperFin (ESF)).
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Intel has confirmed that the Golden Cove architecture will be fabricated on their [[10 nm process]] (10 nm Enhanced SuperFin (ESF)).
  
 
== Architecture ==
 
== Architecture ==
 
=== Key changes from {{\\|Willow Cove}}===
 
=== Key changes from {{\\|Willow Cove}}===
 
* Performance improvements
 
* Performance improvements
** Strong IPC improvement (19%)
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** Strong IPC improvement
** AI workload improvement (AMX)
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** AI workload improvement
 
** Network/5G performance improvements
 
** Network/5G performance improvements
 
* New security features
 
* New security features
* Front-End
 
** Add 2 simple decoders from 5 but canceled the complex decoder design as it is no longer practical and complex instructions can now be handled by macro uop fusion independently in instruction sequencer, total is now 6 simple decoders
 
** x2.5 BTB at 12K entries
 
** 2x pages 4k
 
** Add more 256 and 32 pages of 2M and 4MB respectively
 
* Back-End
 
** Increased ROB 512 (from 352 Sunny Cove)
 
** Add 2 execution port for a total 12
 
* Execution Engine
 
** Add one ALU and LEA for a total 5
 
 
{{expand list}}
 
{{expand list}}
  
 
== Bibliography ==
 
== Bibliography ==
 
* Intel Architecture Day 2018, December 11, 2018
 
* Intel Architecture Day 2018, December 11, 2018
* Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
 

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codenameGolden Cove +
designerIntel +
first launchedNovember 4, 2021 +
full page nameintel/microarchitectures/golden cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameGolden Cove +
process10 nm (0.01 μm, 1.0e-5 mm) +