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{{intel title|Gen10|arch}}
+
{{intel title|Gen10 LP|arch}}
 
{{microarchitecture
 
{{microarchitecture
 
| atype            = GPU
 
| atype            = GPU
| name            = Gen10
+
| name            = Gen10 LP
 
| designer        = Intel
 
| designer        = Intel
 
| manufacturer    = Intel
 
| manufacturer    = Intel
| introduction    = 2018
+
| introduction    = 2017
 
| phase-out        =
 
| phase-out        =
 
| process          = 10 nm
 
| process          = 10 nm
  
 
| succession      = Yes
 
| succession      = Yes
| predecessor      = Gen9.5
+
| predecessor      = Gen9.5 LP
| predecessor link = intel/microarchitectures/gen9.5
+
| predecessor link = intel/microarchitectures/gen9.5_lp
| successor        = Gen11
+
| successor        = Gen11 LP
| successor link  = intel/microarchitectures/gen11
+
| successor link  = intel/microarchitectures/gen11_lp
 
}}
 
}}
'''Gen10''' (''Generation 10'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Cannonlake}}-based microprocessors. Gen10 is the successor to {{\\|Gen9.5}} used by {{\\|Kaby Lake}}.
+
'''Gen10 LP''' (''Generation 10 Low Power'') is the [[microarchitecture]] for [[Intel]]'s [[graphics processing unit]] utilized by {{\\|Cannonlake}}-based microprocessors. Gen10 LP is the successor to {{\\|Gen9.5 LP}} used by {{\\|Kaby Lake}}.
 
 
The display portion of this architecture is also used by {{\\|Goldmont Plus}}, however, it still uses {{\\|Gen9.5}} for the execution units.
 
 
 
'''Due to Intel skipping over {{\\|Cannon Lake}}, Gen10 graphics have never been productized.'''
 
 
 
== Codenames ==
 
[[File:iris graphics logo.svg|right|200px]]
 
Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional [[eDRAM]] side cache.
 
{| class="wikitable"
 
|-
 
! Code Name !! Description
 
|-
 
| GT1 || Contains 1 slice with 24 execution units.
 
|-
 
| GT2 || Contains 1 slice with 40 execution units.
 
|-
 
| GT3 || Contains 2 slices with 48 execution units.
 
|-
 
| GT3e || Contains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.
 
|-
 
| GT4e || Contains 3 slices with 72 execution units. Has an additional [[eDRAM]] side cache.
 
|}
 
 
 
== Architecture ==
 
 
 
=== Key changes from {{\\|Gen9.5}} ===
 
* Display
 
** HDMI 2.0 (from 1.4a)
 
*** 2160p (4K) @ 60 Hz (from 24 Hz)
 
* Execution Units
 
** Double EU for graphics tier 1 (GT1) (24 Execution Units, 2x EUs)
 
** Higher EU count for graphics tier 2 (GT2) (40 Execution Units, 1.7x EUs)
 
 
 
{{expand list}}
 
 
 
== Overview ==
 
Gen10 graphics were originally intended to ship with {{\\|Cannon Lake}}-based chips, however, continuous issues and prolong delays with their [[10 nm process]] as forced Intel to skip over this design. No Gen10-based chips have ever been productized.
 
 
 
== See also ==
 
* {{\\|Cannon Lake}}
 

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codenameGen10 +
designerIntel +
first launched2018 +
full page nameintel/microarchitectures/gen10 +
instance ofmicroarchitecture +
manufacturerIntel +
microarchitecture typeGPU +
nameGen10 +
process10 nm (0.01 μm, 1.0e-5 mm) +