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'''Cascade Lake''' ('''CSL'''/'''CLX''') is [[Intel]]'s successor to {{\\|Skylake (server)|Skylake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's {{intel|PAO}} model. | '''Cascade Lake''' ('''CSL'''/'''CLX''') is [[Intel]]'s successor to {{\\|Skylake (server)|Skylake}}, a [[14 nm]] [[microarchitecture]] for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's {{intel|PAO}} model. | ||
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| {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | | {{intel|Cascade Lake W|l=core}} || CSL-W || || Enterprise/Business workstations | ||
|- | |- | ||
− | | {{intel|Cascade Lake SP|l=core}} || | + | | {{intel|Cascade Lake SP|l=core}} || CSL-SP || || Server Scalable Processors |
|- | |- | ||
− | | {{intel|Cascade Lake AP|l=core}} || | + | | {{intel|Cascade Lake AP|l=core}} || CSL-AP || || Server Advanced Processors |
|} | |} | ||
== Brands == | == Brands == | ||
− | Cascade Lake is sold under | + | Cascade Lake is sold under four different families. |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
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|- | |- | ||
! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{intel|Turbo Boost|TBT}} !! {{x86|AVX-512}} !! AVX-512 Units !! {{intel|Ultra Path Interconnect|UPI}} links !! Scalability | ||
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|- | |- | ||
| [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | | [[File:xeon bronze (2017).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tchk|yes}} || 1 || 2 || Up to 2 | ||
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| [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || 4-28 || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8 | | [[File:xeon platinum (2017).png|50px]] || {{intel|Xeon Platinum}} || style="text-align: left;" | Highest performance / flexibility || 4-28 || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || 2 || 3 || Up to 8 | ||
|} | |} | ||
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== Release Dates == | == Release Dates == | ||
− | Cascade Lake was released on April 2 | + | Cascade Lake was released on April 2, 2019. |
== Process Technology == | == Process Technology == | ||
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*** Hardware mitigations for {{cve|CVE-2018-3620}}/{{cve|CVE-2018-3646}} (L1 Terminal Fault, Foreshadow) | *** Hardware mitigations for {{cve|CVE-2018-3620}}/{{cve|CVE-2018-3646}} (L1 Terminal Fault, Foreshadow) | ||
*** Hardware mitigations for {{cve|CVE-2018-12130}}/{{cve|CVE-2018-12126}}/{{cve|CVE-2018-12127}}/{{cve|CVE-2019-11091}} (MDS; MFBDS, RIDL, MSBDS, Fallout, MLPDS, MDSUM) | *** Hardware mitigations for {{cve|CVE-2018-12130}}/{{cve|CVE-2018-12126}}/{{cve|CVE-2018-12127}}/{{cve|CVE-2019-11091}} (MDS; MFBDS, RIDL, MSBDS, Fallout, MLPDS, MDSUM) | ||
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* Integrated Memory Controller | * Integrated Memory Controller | ||
** Added support for [[persistent memory]] | ** Added support for [[persistent memory]] | ||
*** Support for DDR-T / Optane DIMMs | *** Support for DDR-T / Optane DIMMs | ||
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* Memory | * Memory | ||
** Higher data rate (2933 MT/s, up from 2666 MT/s) | ** Higher data rate (2933 MT/s, up from 2666 MT/s) | ||
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** Extended memory support for up to 2 TiB per socket (up from 1.5 TiB) | ** Extended memory support for up to 2 TiB per socket (up from 1.5 TiB) | ||
** Large memory support for up to 4.5 TiB per socket | ** Large memory support for up to 4.5 TiB per socket | ||
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====New instructions ==== | ====New instructions ==== | ||
Cascade Lake introduced a number of {{x86|extensions|new instructions}}: | Cascade Lake introduced a number of {{x86|extensions|new instructions}}: | ||
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===== LCC SoC ===== | ===== LCC SoC ===== | ||
:[[File:skylake sp lcc block diagram.svg|500px]] | :[[File:skylake sp lcc block diagram.svg|500px]] | ||
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===== HCC SoC ===== | ===== HCC SoC ===== | ||
:[[File:skylake sp hcc block diagram.svg|600px]] | :[[File:skylake sp hcc block diagram.svg|600px]] | ||
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===== Individual Core ===== | ===== Individual Core ===== | ||
<small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | <small>The high-level core architecture is identical to that of {{\\|Skylake (server)#Individual Core|Skylake}}.</small> | ||
− | :[[File:skylake server block diagram.svg| | + | :[[File:skylake server block diagram.svg|950px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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*** 2,048 sets, 12-way set associative | *** 2,048 sets, 12-way set associative | ||
* DRAM | * DRAM | ||
− | ** 6 channels of DDR4, up to | + | ** 6 channels of DDR4, up to 2666 MT/s |
*** RDIMM and LRDIMM | *** RDIMM and LRDIMM | ||
− | *** bandwidth of | + | *** bandwidth of 21.33 GB/s |
− | *** aggregated bandwidth of | + | *** aggregated bandwidth of 128 GB/s |
Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | Cascade Lake TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). | ||
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**** fixed partition | **** fixed partition | ||
*** 1G page translations: | *** 1G page translations: | ||
− | **** 4 entries; | + | **** 4 entries; fully associative |
**** fixed partition | **** fixed partition | ||
** STLB | ** STLB | ||
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== Higher core-count multi-chip processors == | == Higher core-count multi-chip processors == | ||
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{{main|intel/cores/cascade_lake_ap|l1=Cascade Lake Advanced Performance}} | {{main|intel/cores/cascade_lake_ap|l1=Cascade Lake Advanced Performance}} | ||
− | Intel introduced a number of new products, code name {{intel|Cascade Lake Advanced Performance|l=core}}, which doubled the core count. Intel achieved this by packaging two extreme core count (XCC) dies together on the same substrate in a BGA package. The two dies are interconnected through 1 {{intel|UPI}} link | + | Intel introduced a number of new products, code name {{intel|Cascade Lake Advanced Performance|l=core}}, which doubled the core count. Intel achieved this by packaging two extreme core count (XCC) dies together on the same substrate in a BGA package. The two dies are interconnected through 1 {{intel|UPI}} link. This was done to support a fully-connected system in a 2-way SMP system which is where those chips are designed to go. In those systems, every die is interconnected to every other die (four in total) over a {{intel|UPI}} link. With to dies per package, each CPU exposes 12 DDR4 memory channels and x40 PCIe Gen3 lanes. |
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=== Package === | === Package === | ||
− | Cascade Lake AP uses a high-density high-performance ball grid array (BGA) package. It has 5,903 balls at a 0.99 mm pitch. There are two separate power corridors for performance and power reasons. It uses a single heat spreader designed to cover the entire TDP range for all processor models. In total, each package exposes 12 | + | Cascade Lake AP uses a high-density high-performance ball grid array (BGA) package. It has 5,903 balls at a 0.99 mm pitch. There are two separate power corridors for performance and power reasons. It uses a single heat spreader designed to cover the entire TDP range for all processor models. In total, each package exposes 12 chanels DDR4 supporting rates of up to 2933 MT/s as well as 4 {{intel|UPI}} links operating at 10.4 GT/s. |
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{{clear}} | {{clear}} | ||
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== New Technologies == | == New Technologies == | ||
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=== Speed Select Technology === | === Speed Select Technology === | ||
{{main|intel/speed select technology|l1=Speed Select Technology}} | {{main|intel/speed select technology|l1=Speed Select Technology}} | ||
− | + | {{empty section}} | |
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− | === | + | == Persistent Memory Support == |
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− | + | Intel Optane DC Persistent Memory (DCPMM) (Codename: Apache Pass) will be supported starting with Cascade Lake. The next architecture/codename is Barlow Pass. | |
− | The | ||
− | + | DCPMM is designed to improve overall Data Center (DC) system performance and to lower latencies by putting more data closer to the processor on NV Media. | |
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− | + | DCPMM Modules are DDR4 socket compatible, and will be available in capacities up to 512GB/Module. | |
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− | == | + | === DCPMM Modules Sizes === |
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− | + | * 128GB | |
+ | * 256GB | ||
+ | * 512GB | ||
− | + | === DCPMM Specs === | |
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− | + | * Capacity Per CPU: 3TB | |
− | + | * Speed 2666MT/sec | |
− | + | * Close to DRAM latency | |
− | + | * Cache line size access | |
− | + | * Operational Modes | |
+ | ** APP Direct Mode - low latency persistent memroy | ||
+ | ** Memory Mode - Used as DDR4 DRAM | ||
== Scalability == | == Scalability == | ||
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<div style="text-align: center;">'''8-way SMP; 3 UPI links'''<br><br>[[File:cascade lake sp 8-way 3 upi.svg|400px]]</div> | <div style="text-align: center;">'''8-way SMP; 3 UPI links'''<br><br>[[File:cascade lake sp 8-way 3 upi.svg|400px]]</div> | ||
</div> | </div> | ||
+ | |||
+ | == Processor Model Number Suffixes == | ||
+ | |||
+ | * T = High Tcase | ||
+ | * C/Y = Speed Select (It was planned as "C" but was changed to "Y" Later, all "C" Models are now "Y" Models for Speed Select) | ||
+ | * N = NFV Optimized | ||
+ | * M = Medium memory tier | ||
+ | * U = Single Socket | ||
+ | * S = Search Optimized | ||
+ | * L = Large Memory Tier | ||
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== All Cascade Lake Chips == | == All Cascade Lake Chips == | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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== Documents == | == Documents == | ||
* [[:File:cascade-lake-advanced-performance-press-deck.pdf|Cascade Lake Advanced Performance]] | * [[:File:cascade-lake-advanced-performance-press-deck.pdf|Cascade Lake Advanced Performance]] |
Facts about "Cascade Lake - Microarchitectures - Intel"
codename | Cascade Lake + |
core count | 2 +, 4 +, 6 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 22 +, 24 +, 26 +, 28 +, 32 +, 48 + and 56 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |