From WikiChip
Editing intel/microarchitectures/airmont
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{intel title|Airmont|arch}} | {{intel title|Airmont|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | |||
| name = Airmont | | name = Airmont | ||
− | |||
| manufacturer = Intel | | manufacturer = Intel | ||
| introduction = 2015 | | introduction = 2015 | ||
Line 18: | Line 16: | ||
| speculative = Yes | | speculative = Yes | ||
| renaming = Yes | | renaming = Yes | ||
− | |isa= | + | | isa = IA-32 |
− | + | | isa 2 = x86-64 | |
− | | | + | | stages = 14 |
− | | stages | ||
| issues = 2 | | issues = 2 | ||
| inst = Yes | | inst = Yes | ||
| feature = | | feature = | ||
− | | extension = | + | | extension = MMX |
− | | extension 2 = | + | | extension 2 = SSE |
− | | extension 3 = | + | | extension 3 = SSE2 |
− | | extension 4 = | + | | extension 4 = SSE3 |
− | | extension 5 = | + | | extension 5 = SSSE3 |
− | | extension 6 = | + | | extension 6 = SSE4 |
| extension 7 = SSE4.1 | | extension 7 = SSE4.1 | ||
| extension 8 = SSE4.2 | | extension 8 = SSE4.2 | ||
− | | extension 9 = | + | | extension 9 = VT-x |
− | | extension 10 = AES | + | | extension 10 = AES-NI |
− | | extension 11 = | + | | extension 11 = CLMUL |
− | | extension 12 = | + | | extension 12 = RDRAND |
| cache = Yes | | cache = Yes | ||
− | | l1i = 32 | + | | l1i = 32 KB |
| l1i per = Core | | l1i per = Core | ||
| l1i desc = 8-way set associative | | l1i desc = 8-way set associative | ||
− | | l1d = 24 | + | | l1d = 24 KB |
| l1d per = Core | | l1d per = Core | ||
| l1d desc = 6-way set associative | | l1d desc = 6-way set associative | ||
− | | l2 = 1 | + | | l2 = 1 MB |
| l2 per = 2 Cores | | l2 per = 2 Cores | ||
| l2 desc = 16-way set associative | | l2 desc = 16-way set associative | ||
Line 69: | Line 66: | ||
! Platform !! Core !! Target | ! Platform !! Core !! Target | ||
|- | |- | ||
− | | {{intel| | + | | {{intel|Cherry Trail}} || {{intel|Cherry Trail}} || Smartphones, Tablets |
|- | |- | ||
− | | {{intel| | + | | {{intel|Braswell}} || {{intel|Braswell}} || Tablets, PCs |
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
− | |||
− | |||
− | |||
− | |||
== Architecture== | == Architecture== | ||
Line 97: | Line 86: | ||
** Hardware prefetchers | ** Hardware prefetchers | ||
** L1 Cache: | ** L1 Cache: | ||
− | *** 32 | + | *** 32 KB 8-way [[set associative]] instruction, 64 B line size |
− | *** 24 | + | *** 24 KB 6-way set associative data, 64 B line size |
*** Per core | *** Per core | ||
** L2 Cache: | ** L2 Cache: | ||
− | *** 1 | + | *** 1 MB 16-way set associative, 64 B line size |
*** Per 2 cores | *** Per 2 cores | ||
** L3 Cache: | ** L3 Cache: | ||
*** No level 3 cache | *** No level 3 cache | ||
** RAM | ** RAM | ||
− | *** Maximum of | + | *** Maximum of 1GB, 2 GB, and 4 GB |
*** dual 32-bit channels, 1 or 2 ranks per channel | *** dual 32-bit channels, 1 or 2 ranks per channel | ||
Line 132: | Line 121: | ||
<tr><th colspan="12" style="background:#D6D6FF;">Airmont Chips</th></tr> | <tr><th colspan="12" style="background:#D6D6FF;">Airmont Chips</th></tr> | ||
<tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr> | <tr><th colspan="9">Main processor</th><th colspan="3">IGP</th></tr> | ||
− | <tr><th>Model</th><th> | + | <tr><th>Model</th><th>µarch</th><th>Platform</th><th>Core</th><th>Launched</th><th>SDP</th><th>TDP</th><th>Freq</th><th>Max Mem</th><th>Name</th><th>Freq</th><th>Max Freq</th></tr> |
{{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Airmont]] | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Airmont]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
− | |? | + | |?microarchitecture |
|?platform | |?platform | ||
|?core name | |?core name | ||
Line 149: | Line 138: | ||
|format=template | |format=template | ||
|template=proc table 2 | |template=proc table 2 | ||
− | |userparam= | + | |userparam=12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
− | |||
</table> | </table> |
Facts about "Airmont - Microarchitectures - Intel"
codename | Airmont + |
core count | 1 +, 2 +, 4 + and 8 + |
designer | Intel + |
first launched | 2015 + |
full page name | intel/microarchitectures/airmont + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Airmont + |
phase-out | 2017 + |
pipeline stages (max) | 14 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |