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| clock max        = 2.08 MHz
 
| clock max        = 2.08 MHz
 
| package          = DIP40
 
| package          = DIP40
−
 
−
| succession      = Yes
 
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| predecessor      = MCS-8
 
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| predecessor link = intel/mcs-8
 
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| successor        = MCS-85
 
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| successor link  = intel/mcs-85
 
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| successor 2      = MCS-86
 
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| successor 2 link = intel/mcs-86
 
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| successor 3      = MCS-88
 
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| successor 3 link = intel/mcs-88
 
 
}}
 
}}
 
The '''MCS-80''' ('''Micro Computer Set-80''') was a family of {{arch|8}} microprocessor chipsets developed by [[Intel]]. Introduced on April, 1974, the MCS-80 featured the {{\|8080}} CPU, the forefather of all modern [[x86]]-based microprocessors.
 
The '''MCS-80''' ('''Micro Computer Set-80''') was a family of {{arch|8}} microprocessor chipsets developed by [[Intel]]. Introduced on April, 1974, the MCS-80 featured the {{\|8080}} CPU, the forefather of all modern [[x86]]-based microprocessors.
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! Part !! Frequency !! Description
 
! Part !! Frequency !! Description
 
|-
 
|-
−
| {{\|8080}} || 500 kHz - 2.08 MHz || MPU, Original, has compatibility issues with TTL
+
| {{\|8080}} || 500 kHz - 2.08 MHz || MPU, Original, has compatibility with TTL
 
|-
 
|-
 
| {{\|8080A-1}} || 500 kHz - 3.12 MHz || MPU
 
| {{\|8080A-1}} || 500 kHz - 3.12 MHz || MPU
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|-
 
|-
 
| {{\|8238}} || || system controller & bus driver
 
| {{\|8238}} || || system controller & bus driver
−
|-
 
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| {{\|8257}} || || Programmable DMA Controller
 
−
|-
 
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| {{\|8259}} || || Programmable Interrupt Controller
 
−
|-
 
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| {{\|8279}} || || Programmable Keyboard/Display Controller
 
−
|-
 
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| {{\|8271}} || || Programmable Floppy Disk Controller
 
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|-
 
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| {{\|8222}} || || Dynamic RAM Refresh Controller
 
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|-
 
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| {{\|8205}} || || 1 Of 8 Binary Decoder
 
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|-
 
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| {{\|8210}} || || TTL To MOS Shifter & High Voltage Clock Driver
 
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|-
 
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| {{\|8212}} || || 8 Bit I/O Port
 
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|-
 
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| {{\|8214}} || || Priority Interrupt Control Unit
 
−
|-
 
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| {{\|8216}} || || 4 Bit Parallel Bidirectional Bus Driver
 
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|-
 
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| {{\|8251A}} || || Improved Programmable Communication Interface
 
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|-
 
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| {{\|8253}} || || Programmable Interval Timer
 
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|-
 
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| {{\|8255}} || || Programmable Peripheral Interface
 
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|-
 
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| {{\|8255A}} || || Improved Programmable Peripheral Interface
 
 
|}
 
|}
  
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|-
 
|-
 
| {{intel|2316E}} || 2048x8 bit || ROM
 
| {{intel|2316E}} || 2048x8 bit || ROM
−
|-
 
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| {{intel|2114}} || 1024x4 bit || SRAM
 
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|-
 
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| {{intel|2116}} || 16384x1 bit || DRAM
 
 
|}
 
|}
  
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=== ISA ===
 
=== ISA ===
 
{{empty section}}
 
{{empty section}}
−
== Designers ==
 
−
Lead designers for the MCS-80 are:
 
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* [[designer::Federico Faggin]]
 
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* [[designer::Masatoshi Shima]]
 
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* [[designer::Stan Mazor]]
 
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== Documents ==
 
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* [[:File:MCS-80 Users Manual (Oct 1977).pdf|MCS-80 Users Manual, Oct 1977]]
 
 
== See Also ==
 
== See Also ==
 
* {{intel|MCS-4}}
 
* {{intel|MCS-4}}

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Facts about "MCS-80 - Intel"
RDF feed
designerIntel +, Federico Faggin +, Masatoshi Shima + and Stan Mazor +
full page nameintel/mcs-80 +
instance ofmicroprocessor family +
instruction set architecture8080 +
main designerIntel +
manufacturerIntel +
nameIntel MCS-80 +
packageDIP40 +
process6,000 nm (6 μm, 0.006 mm) +
technologynMOS +
word size8 bit (1 octets, 2 nibbles) +