From WikiChip
Editing ibm/microarchitectures/z14
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 21: | Line 21: | ||
|predecessor=z13 | |predecessor=z13 | ||
|predecessor link=ibm/microarchitectures/z13 | |predecessor link=ibm/microarchitectures/z13 | ||
− | |||
− | |||
}} | }} | ||
'''z14''' is the successor to {{\\|z13}}, a [[14 nm]] [[z/Architecture]] mainframe microarchitecture designed by [[IBM]] and introduced in 2017. | '''z14''' is the successor to {{\\|z13}}, a [[14 nm]] [[z/Architecture]] mainframe microarchitecture designed by [[IBM]] and introduced in 2017. | ||
Line 89: | Line 87: | ||
− | + | Every mainframe have two frames that are bolted together. Frames are built to Electronic Industries Alliance (EIA) standards and are 42U EIA frames. Viewed from the front, the right side is called '''Frame A''' while the left side is called '''Frame Z'''. | |
==== Z Frame ==== | ==== Z Frame ==== | ||
Line 145: | Line 143: | ||
=== Central Processor (CP) Chip === | === Central Processor (CP) Chip === | ||
[[File:z14 next to dime.png|right|200px]] | [[File:z14 next to dime.png|right|200px]] | ||
− | * GlobalFoundries [[14 nm process|14HP Process]] | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
Line 152: | Line 150: | ||
* 6,100,000,000 transistors | * 6,100,000,000 transistors | ||
* 14.4 miles of copper wire | * 14.4 miles of copper wire | ||
− | * 26.5 x 27.8 mm | + | * 26.5 x 27.8 mm die |
− | ** 736.7 mm² | + | ** 736.7 mm² die size |
** 18,581 power pins | ** 18,581 power pins | ||
** 1,505 signal pins | ** 1,505 signal pins | ||
− | |||
− | |||
Line 188: | Line 184: | ||
=== System Controller (SC) Chip === | === System Controller (SC) Chip === | ||
[[File:z14sc next to a dime.png|right|200px]] | [[File:z14sc next to a dime.png|right|200px]] | ||
− | * GlobalFoundries [[14 nm process|14HP Process]] | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
Line 198: | Line 194: | ||
− | |||
:: [[File:ibm z14 sc floor plan.png|650px]] | :: [[File:ibm z14 sc floor plan.png|650px]] | ||
− | |||
− | |||
− | |||
− |
Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |