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|predecessor=z13 | |predecessor=z13 | ||
|predecessor link=ibm/microarchitectures/z13 | |predecessor link=ibm/microarchitectures/z13 | ||
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}} | }} | ||
− | '''z14''' is the successor to {{\\|z13}}, a [[14 nm]] | + | '''z14''' is the successor to {{\\|z13}}, a [[14 nm]] microarchitecture designed by [[IBM]] and introduced in 2017 for their [[z/Architecture]] mainframes. |
==Process Technology== | ==Process Technology== | ||
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− | + | Every mainframe have two frames that are bolted together. Frames are built to Electronic Industries Alliance (EIA) standards and are 42U EIA frames. Viewed from the front, the right side is called '''Frame A''' while the left side is called '''Frame Z'''. | |
==== Z Frame ==== | ==== Z Frame ==== | ||
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== System == | == System == | ||
[[File:z14 drawer.svg|right|400px]] | [[File:z14 drawer.svg|right|400px]] | ||
− | + | The IBM z14 mainframe consists of a number of drawers. A drawer is simply a cluster of processors and chipsets. Each drawer consists of two clusters of three processing units (PUs) each and a single system controller (SC) chip. A full drawer can thus have a total of six processors and a single system controller. The SC chip can links one drawer to another for up to four drawers in the max z14 mainframe system. In a max configuration the z14 can have a total of 24 processors. With up to 10 cores per processor, a maximum-configured system can have a total of 240 cores. | |
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− | The IBM z14 mainframe consists of a number of drawers. A drawer is simply a cluster of processors and chipsets. Each drawer consists of two clusters of three | ||
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− | The SC chip can links one drawer to another for up to four drawers in the max z14 mainframe system. In a max configuration | ||
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== Die == | == Die == | ||
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=== Central Processor (CP) Chip === | === Central Processor (CP) Chip === | ||
[[File:z14 next to dime.png|right|200px]] | [[File:z14 next to dime.png|right|200px]] | ||
− | * GlobalFoundries [[14 nm process|14HP Process]] | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
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* 6,100,000,000 transistors | * 6,100,000,000 transistors | ||
* 14.4 miles of copper wire | * 14.4 miles of copper wire | ||
− | * 26.5 x 27.8 mm | + | * 26.5 x 27.8 mm die |
− | ** 736.7 mm² | + | ** 736.7 mm² die size |
** 18,581 power pins | ** 18,581 power pins | ||
** 1,505 signal pins | ** 1,505 signal pins | ||
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:: [[File:z14 die floor plan.png|650px]] | :: [[File:z14 die floor plan.png|650px]] | ||
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==== Core ==== | ==== Core ==== | ||
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* '''IDU''' - Instruction decode unit | * '''IDU''' - Instruction decode unit | ||
* '''IFB''' - Instruction fetch and branch prediction | * '''IFB''' - Instruction fetch and branch prediction | ||
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=== System Controller (SC) Chip === | === System Controller (SC) Chip === | ||
[[File:z14sc next to a dime.png|right|200px]] | [[File:z14sc next to a dime.png|right|200px]] | ||
− | * GlobalFoundries [[14 nm process|14HP Process]] | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
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:: [[File:ibm z14 sc floor plan.png|650px]] | :: [[File:ibm z14 sc floor plan.png|650px]] | ||
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Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |