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|predecessor=z13 | |predecessor=z13 | ||
|predecessor link=ibm/microarchitectures/z13 | |predecessor link=ibm/microarchitectures/z13 | ||
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}} | }} | ||
− | '''z14''' is | + | '''z14''' is a [[z/Architecture]]-based microarchitecture designed by [[IBM]] and introduced in 2017 for their {{ibm|z14}} processors and mainframes. The z14 microarchitecture replaced the {{\\|z13}}. |
==Process Technology== | ==Process Technology== | ||
− | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process | + | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM at what used to be their East Fishkill, New York fab which has since been sold to GlobalFoundries. |
== Release Dates == | == Release Dates == | ||
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− | + | Every mainframe have two frames that are bolted together. Frames are built to Electronic Industries Alliance (EIA) standards and are 42U EIA frames. Viewed from the front, the right side is called '''Frame A''' while the left side is called '''Frame Z'''. | |
==== Z Frame ==== | ==== Z Frame ==== | ||
− | {| class="wikitable | + | {| class="wikitable" |
|- | |- | ||
| || At the top of the frame is an optional overhead power cabling solution. There are top exit options for fiber optic cables and other ethernet solutions such as [[FICON]], [[OSA]], 12x [[InfiniBand]], 1x InfiniBand, ICA, zHyperLink Express, Coupling Express LR, and RoCE. | | || At the top of the frame is an optional overhead power cabling solution. There are top exit options for fiber optic cables and other ethernet solutions such as [[FICON]], [[OSA]], 12x [[InfiniBand]], 1x InfiniBand, ICA, zHyperLink Express, Coupling Express LR, and RoCE. | ||
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|- | |- | ||
| [[File:ibm z14 power supplies.png|250px]] | | [[File:ibm z14 power supplies.png|250px]] | ||
− | | | + | | Additionally, at the top are a large set of Bulk power regulators (BPRs). The number of BPRs in the frame will depend on the exact configuration of the unit. |
|- | |- | ||
| [[File:ibm z14 io drawers.png|250px]] | | [[File:ibm z14 io drawers.png|250px]] | ||
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==== A Frame ==== | ==== A Frame ==== | ||
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|- | |- | ||
| [[File:ibm z14 se.png|250px]] | | [[File:ibm z14 se.png|250px]] | ||
− | | | + | | At the two are two support elements (SE) 1U servers. |
|- | |- | ||
| [[File:ibm z14 pcie 5.png|250px]] | | [[File:ibm z14 pcie 5.png|250px]] | ||
− | | | + | | There is one optional PCIe I/O drawer. |
|- | |- | ||
| [[File:ibm z14 ctrl hub.png|250px]] | | [[File:ibm z14 ctrl hub.png|250px]] | ||
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| Two radiator pumps or two Water Conditioning Units (WCUs) in the case of water cooling. | | Two radiator pumps or two Water Conditioning Units (WCUs) in the case of water cooling. | ||
|} | |} | ||
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== Die == | == Die == | ||
− | + | === Core === | |
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Below is a layout of a single [[physical core]]: | Below is a layout of a single [[physical core]]: | ||
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* '''IDU''' - Instruction decode unit | * '''IDU''' - Instruction decode unit | ||
* '''IFB''' - Instruction fetch and branch prediction | * '''IFB''' - Instruction fetch and branch prediction | ||
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+ | === Single-chip module (SCM) === | ||
+ | IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either: | ||
+ | |||
+ | * 1x Processor Unit (PU) | ||
+ | * 1x System Controller (SC) | ||
+ | |||
+ | === Central Processor (CP) Chip === | ||
+ | [[File:z14 next to dime.png|right|200px]] | ||
+ | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] | ||
+ | ** CMOS FinFET SOI | ||
+ | ** 17 Metal Layers | ||
+ | * [[deca-core]] (10 Processor Units (PUs)) | ||
+ | * 5.2 GHz (192 ps cycle time) | ||
+ | * 6,100,000,000 transistors | ||
+ | * 14.4 miles of copper wire | ||
+ | * 26.5 x 27.8 mm die | ||
+ | ** 736.7 mm² die size | ||
+ | ** 18,581 power pins | ||
+ | ** 1,505 signal pins | ||
+ | |||
+ | |||
+ | :: [[File:z14 die floor plan.png|650px]] | ||
=== System Controller (SC) Chip === | === System Controller (SC) Chip === | ||
[[File:z14sc next to a dime.png|right|200px]] | [[File:z14sc next to a dime.png|right|200px]] | ||
− | * GlobalFoundries [[14 nm process|14HP Process]] | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
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:: [[File:ibm z14 sc floor plan.png|650px]] | :: [[File:ibm z14 sc floor plan.png|650px]] | ||
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Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |