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|l1i=128 KiB | |l1i=128 KiB | ||
|l1d=128 KiB | |l1d=128 KiB | ||
− | |predecessor= | + | |predecessor=z12 |
|predecessor link=ibm/microarchitectures/z13 | |predecessor link=ibm/microarchitectures/z13 | ||
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}} | }} | ||
− | '''z14''' | + | '''z14''' was a [[z/Architecture]]-based microarchitecture designed by [[IBM]] and introduced in 2017 for their {{ibm|z14}} processors and mainframes. The z14 microarchitecture replaced the {{\\|z13}}. |
==Process Technology== | ==Process Technology== | ||
− | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process | + | z14-based microprocessors are manufactured on [[GlobalFoundries]]'s [[14 nm process|14 nm]] (14HP) [[FinFET]] [[Silicon-On-Insulator]] (SOI) process. The process was designed by IBM at what used to be their East Fishkill, New York fab which has since been sold to GlobalFoundries. |
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− | IBM | ||
== Architecture == | == Architecture == | ||
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=== Key changes from {{\\|z13}} === | === Key changes from {{\\|z13}} === | ||
* [[14 nm process]] (from [[22 nm process|22 nm]]) | * [[14 nm process]] (from [[22 nm process|22 nm]]) | ||
− | + | * Higher clock frequency (5.2 GHz from 5 GHz) | |
− | * Higher clock frequency (5.2 GHz from 5 GHz | ||
* Higher scalability | * Higher scalability | ||
** Up to 170-way multiprocessing (from 141-way) | ** Up to 170-way multiprocessing (from 141-way) | ||
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** Faster branch wakeup | ** Faster branch wakeup | ||
** Improved instruction delivery | ** Improved instruction delivery | ||
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* Cache | * Cache | ||
** New directory design | ** New directory design | ||
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** L3$ increased to 128 MiB/CP (from 64 MiB/CP; 100% increase) | ** L3$ increased to 128 MiB/CP (from 64 MiB/CP; 100% increase) | ||
** New 672 MiB/drawer of shared L4 | ** New 672 MiB/drawer of shared L4 | ||
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* Central Processor Assist for Cryptographic Function (CPACF) | * Central Processor Assist for Cryptographic Function (CPACF) | ||
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** New support for [[SHA-3]] standard | ** New support for [[SHA-3]] standard | ||
− | {{expand | + | {{expand section}} |
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== Overview == | == Overview == | ||
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== Die == | == Die == | ||
− | + | === Core === | |
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Below is a layout of a single [[physical core]]: | Below is a layout of a single [[physical core]]: | ||
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* '''IDU''' - Instruction decode unit | * '''IDU''' - Instruction decode unit | ||
* '''IFB''' - Instruction fetch and branch prediction | * '''IFB''' - Instruction fetch and branch prediction | ||
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+ | === Single-chip module (SCM) === | ||
+ | IBM's z14 Single-Chip Module (SCM) consists of a multi-layer metal substrate module that includes either: | ||
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+ | * 1x Processor Unit (PU) | ||
+ | * 1x System Controller (SC) | ||
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+ | === Processor Unit (PU) Chip === | ||
+ | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] | ||
+ | ** CMOS FinFET SOI | ||
+ | ** 17 Metal Layers | ||
+ | * 25.3 x 27.5 mm die | ||
+ | * 695.75 mm² die size | ||
+ | * [[deca-core]] | ||
+ | * 5.2 GHz (192 ps cycle time) | ||
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+ | :: [[File:z14 die floor plan.png|650px]] | ||
=== System Controller (SC) Chip === | === System Controller (SC) Chip === | ||
− | [[ | + | * [[IBM]]'s developed (now GlobalFoundries) [[14 nm process|14HP Process]] |
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** CMOS FinFET SOI | ** CMOS FinFET SOI | ||
** 17 Metal Layers | ** 17 Metal Layers | ||
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:: [[File:ibm z14 sc floor plan.png|650px]] | :: [[File:ibm z14 sc floor plan.png|650px]] | ||
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Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |