From WikiChip
Editing ibm/microarchitectures/z14
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 173: | Line 173: | ||
− | * | + | * L2 - L2I$ + L2D$ |
− | * | + | * PC + TP - Core pervasive unit (instrumentation/error collection) + Trap |
− | * | + | * LSU - Load-store unit (+ L1D$) |
− | * | + | * XU - Translation unit ([[translation lookaside buffer|TLB]] + [[dynamic address translation|DAT]]) |
− | * | + | * ICM - Instruction cache & merge |
− | * | + | * COP - Dedicated Co-Processor |
− | * | + | * FXU - Fixed-point unit |
− | * | + | * VFU - Vector and Floating point Unit |
− | * | + | * ISU - Instruction sequence unit |
− | * | + | * RU - Recovery unit |
− | * | + | * IDU - Instruction decode unit |
− | * | + | * IFB - Instruction fetch and branch prediction |
=== System Controller (SC) Chip === | === System Controller (SC) Chip === |
Facts about "z14 - Microarchitectures - IBM"
codename | z14 + |
core count | 7 +, 8 +, 9 + and 10 + |
designer | IBM + |
first launched | July 17, 2017 + |
full page name | ibm/microarchitectures/z14 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |