Editing hisilicon/kunpeng/hi1612

{{hisilicon title|Hi1612}}
{{chip
|name=Hi1612
|no image=Yes
|designer=HiSilicon
|designer 2=ARM Holdings
|manufacturer=TSMC
|model number=Hi1612
|market=Server
|first announced=June 4, 2016
|first launched=June 4, 2016
|family=Hi16xx
|frequency=2,100 MHz
|isa=ARMv8
|isa family=ARM
|microarch=Cortex-A57
|core name=Cortex-A57
|process=16 nm
|technology=CMOS
|word size=64 bit
|core count=32
|thread count=32
|max cpus=2
|max memory=256 GiB
}}
'''Hi1612''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2016. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.

== Cache ==
{{main|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A57 § Cache}}
{{cache size
|l1 cache=2.5 MiB
|l1i cache=1.5 MiB
|l1i break=32x48 KiB
|l1i desc=8-way set associative
|l1d cache=1 MiB
|l1d break=32x32 KiB
|l1d desc=8-way set associative
|l2 cache=8 MiB
|l2 break=32x256 KiB
|l2 desc=8-way set associative
|l3 cache=32 MiB
|l3 break=32x1 MiB
|l3 desc=16-way set associative
}}

== Memory controller ==
{{memory controller
|type=DDR4-2133
|ecc=Yes
|max mem=256 GiB
|controllers=1
|channels=4
|width=64 bit
|max bandwidth=63.58 GiB/s
|bandwidth schan=15.89 GiB/s
|bandwidth dchan=31.79 GiB/s
|bandwidth qchan=63.58 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=16
|pcie config=2x8
}}
}}
== Features ==
{{arm features
|thumb=No
|thumb2=No
|thumbee=No
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|trustzone=No
|jazelle=No
|wmmx=No
|wmmx2=No
|pmuv3=No
|crc32=Yes
|crypto=No
|fp=No
|fp16=No
|profile=No
|ras=No
|simd=No
|rdm=No
}}

== Utilizing devices ==
* [[used by::HiSilicon D03]]
* [[used by::Huawei Taishan 2180]]

{{expand list}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Hi1612 - HiSilicon#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count	32 +
core name	Cortex-A57 +
designer	HiSilicon + and ARM Holdings +
family	Hi16xx +
first announced	June 4, 2016 +
first launched	June 4, 2016 +
full page name	hisilicon/kunpeng/hi1612 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	16-way set associative +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	June 4, 2016 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth	63.58 GiB/s (65,105.92 MiB/s, 68.269 GB/s, 68,268.505 MB/s, 0.0621 TiB/s, 0.0683 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A57 +
model number	Hi1612 +
name	Hi1612 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2133 +
technology	CMOS +
thread count	32 +
used by	HiSilicon D03 + and Huawei Taishan 2180 +
word size	64 bit (8 octets, 16 nibbles) +