Editing fujitsu/sparc64

{{fujitsu title|SPARC64}}
{{ic family
| title             = SPARC64
| image             =  
| caption           = 
| no image          = Yes
| developer 2       = HAL Computer Systems
| developer         = Fujitsu
| manufacturer      = Fujitsu
| manufacturer 2    = TSMC
| type              = Microprocessors
| first announced   = November, 1995
| first launched    = November, 1995
| arch              = 
| isa               = 
| microarch         = SPARC64*
| word              = 64 bit
| proc              = 400 nm
| proc 2            = 350 nm
| proc 3            = 250 nm
| proc 4            = 150 nm
| proc 5            = 130 nm
| proc 6            = 90 nm
| proc 7            = 65 nm
| proc 8            = 45 nm
| proc 9            = 40 nm
| proc 10           = 28 nm
| proc 11           = 20 nm
| tech              = CMOS
| clock min         = 118 MHz
| clock max         = 4,250 MHz
| package           = 
| socket            = 

| succession       = 
| predecessor      = 
| predecessor link = 
| successor        = 
| successor link   = 
}}
'''SPARC64''' is a family of high-performance {{arch|64}} [[SPARC]] microprocessors designed by [[Fujitsu]] (originally [[HAL Computer Systems|HAL]]'s) since the mid-1990s. Fujitsu's SPARC64-based computer systems are used in their own high-performance [[mission-critical]] [[UNIX]] servers.

== History ==
SPARC64 is a family of high-performance [[SPARC-V9]] microprocessors that has been in continuously active development since the [[1990]]. [[SPARC]] emerged as the one of only two RISC processors to survive in the high-performance market. Fujitsu's SPARC64 origin goes back to a 1990-startup company by the name of [[HAL Computer Systems]] which was established by an ex-IBMer for the sole purpose of designing the fastest 64-bit [[RISC]] processor. 

=== HAL ===
In [[1995]] HAL introduced the first {{\|SPARC64}} processor, just a few short months before [[Sun Microsystems]] introduced their own SPARC-V9 {{arch|64}} microprocessor. The processor, which operated at around 118 MHz and was manufactured on Fujitsu's [[0.4µm process]], found itself in many high-end workstations. Packaged in an [[multi-chip module|MCM]] along with four [[cache]] chips and an [[memory management unit|MMU]], the processors was designed as a {{arch|64}} superscalar [[speculative execution|speculative]] [[out-of-order]]. About a year and half later HAL introduced the {{\|SPARC64 II}} which enjoyed higher performance through higher clock speed from a [[process node]] [[node shrink|shrink]].

HAL's final design was the {{\|SPARC64 GP}} which was fabricated on Fujitsu's [[0.24µm process]]. Around [[2001]] HAL was mostly dissolved with all its assets absorbed into Fujitsu's microelectronics division. The {{\|SPARC64 GP}} was a single-chip design, incorporating the [[memory management unit|MMU]] and cache on-die. It was the first design to incorporate key features that would later be found in all future Fujitsu's SPARC64 chips including [[multiprocessing]] support, multiple cache levels, and ECC support throughout the entire system and bus interface. The SPARC64 GP was the first time Fujitsu utilized their SPARC64 processors in their server class systems: {{fujitsu|GRANPOWER}} and {{fujitsu|PRIMEPOWER}} -series. Through a series of [[node shrinks]] Fujitsu improved the frequency of the GP from an initial speed of just 250 MHz to over 800 MHz for the last few models.

=== Fujitsu ===
Following the folding of HAL around 2001, Fujitsu continued the development of the SPARC64 with the introduction of the {{\|SPARC64 V}}. The {{\|SPARC64 V}} is a radical architectural change from all previous designs. Fujitsu's SPARC64 V pipeline is largely based on their mainframe series (the {{fujitsu|GS|Global Server}} (GS) series).
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== Members ==
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== See also ==
* Sun {{sun|UltraSPARC}}
designer	Fujitsu + and HAL Computer Systems +
first announced	November 1995 +
first launched	November 1995 +
full page name	fujitsu/sparc64 +
instance of	microprocessor family +
main designer	Fujitsu +
manufacturer	Fujitsu + and TSMC +
microarchitecture	SPARC64* +
name	SPARC64 +
process	400 nm (0.4 μm, 4.0e-4 mm) +, 350 nm (0.35 μm, 3.5e-4 mm) +, 250 nm (0.25 μm, 2.5e-4 mm) +, 150 nm (0.15 μm, 1.5e-4 mm) +, 130 nm (0.13 μm, 1.3e-4 mm) +, 90 nm (0.09 μm, 9.0e-5 mm) +, 65 nm (0.065 μm, 6.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) + and 20 nm (0.02 μm, 2.0e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +