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|designer 2=ARM Holdings | |designer 2=ARM Holdings | ||
|manufacturer=DEC | |manufacturer=DEC | ||
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|introduction=February 5, 1996 | |introduction=February 5, 1996 | ||
|process=0.35 µm | |process=0.35 µm | ||
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== History == | == History == | ||
− | The StrongARM microarchitecture started as a collaborative project between [[arm holdings|ARM]] and [[DEC]] in the mid-1990s | + | The StrongARM microarchitecture started as a collaborative project between [[arm holdings|ARM]] and [[DEC]] in the mid-1990s. The primary design goal was to develop a new class of high-performance low-power [[ARM]]-based processors. Earlier ARM architectures were simply insufficiently weak to power more advanced mobile devices such as PDAs and set-tops. Because of the new design goals, StrongARM implemented a number of new techniques not found in previous ARM architectures. |
The historical significance of the StrongARM development cannot be overstated. StrongARM implemented the same [[ARM]] architecture as the {{armh|ARM8}} - {{arm|ARMv4}}. The route ARM took to improve the {{armh|ARM7}} through the {{armh|ARM8}} was to widen the pipeline which allowed for double the speed at the cost of more [[die]] space for an identical [[semiconductor process|process]]. ARM8 was consequently seldom licensed and has largely faded into obscurity. The StrongARM on the other hand, which was design using DEC's own in-house tools and semiconductor process, resulted in performance increase of up to 5 times as much. StrongARM enjoyed a series of design wins such as [[Psion]] 7 Series, [[Apple]]'s MessagePad 2000/2100, Yakumo Alpha PDA, and various PDAs from [[HP]]'s Jornada line. After being sold to [[Intel]] in [[1997]], the architecture {{intel|xscale|was enhanced|l=arch}} and went on to dominate the PDA and light mobile market for close to a decade before being sold to [[Marvell]] just prior to the [[smartphone boom]] in 2006. | The historical significance of the StrongARM development cannot be overstated. StrongARM implemented the same [[ARM]] architecture as the {{armh|ARM8}} - {{arm|ARMv4}}. The route ARM took to improve the {{armh|ARM7}} through the {{armh|ARM8}} was to widen the pipeline which allowed for double the speed at the cost of more [[die]] space for an identical [[semiconductor process|process]]. ARM8 was consequently seldom licensed and has largely faded into obscurity. The StrongARM on the other hand, which was design using DEC's own in-house tools and semiconductor process, resulted in performance increase of up to 5 times as much. StrongARM enjoyed a series of design wins such as [[Psion]] 7 Series, [[Apple]]'s MessagePad 2000/2100, Yakumo Alpha PDA, and various PDAs from [[HP]]'s Jornada line. After being sold to [[Intel]] in [[1997]], the architecture {{intel|xscale|was enhanced|l=arch}} and went on to dominate the PDA and light mobile market for close to a decade before being sold to [[Marvell]] just prior to the [[smartphone boom]] in 2006. | ||
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It should be noted that in order to develop StrongARM, DEC had to license the ability to do so from ARM. This was the first time ARM gave a company an architecture license allowing them to actually design their own [[microarchitecture]] that implements the ARM instruction set. Previously ARM had only offered core licenses which gave a licensee an ARM-designed core they can use but they were not allowed to develop their own design. | It should be noted that in order to develop StrongARM, DEC had to license the ability to do so from ARM. This was the first time ARM gave a company an architecture license allowing them to actually design their own [[microarchitecture]] that implements the ARM instruction set. Previously ARM had only offered core licenses which gave a licensee an ARM-designed core they can use but they were not allowed to develop their own design. | ||
− | It's also interesting to note that [[DEC]] was not doing well financially by [[1997]] with their Hudson fab being considerably underused (with some estimates putting it at only 40% utilization or less). The uncertainty put into question DEC's StrongARM manufacturing abilities which prevented some companies from switching to StrongARM. In early [[1997]] DEC filed a surprised patent infringement lawsuit against [[Intel]] over {{decc|Alpha}}-related patents. Intel consequently countersued claiming DEC violated Intel's property rights. A settlement was eventually reached out of court with both companies signing a 10-year [[cross-licensing agreement]] and in an ironic twist of | + | It's also interesting to note that [[DEC]] was not doing well financially by [[1997]] with their Hudson fab being considerably underused (with some estimates putting it at only 40% utilization or less). The uncertainty put into question DEC's StrongARM manufacturing abilities which prevented some companies from switching to StrongARM. In early [[1997]] DEC filed a surprised patent infringement lawsuit against [[Intel]] over {{decc|Alpha}}-related patents. Intel consequently countersued claiming DEC violated Intel's property rights. A settlement was eventually reached out of court with both companies signing a 10-year [[cross-licensing agreement]] and in an ironic twist of faith as part of a settlement, Intel agreed to buy DEC's semiconductor manufacturing operations for $700 million which included the Hudson, Mass foundry as well as DEC's development operations in Jerusalem, Israel and Austin, Texas. |
== Process Technology == | == Process Technology == | ||
{{see also|0.35 µm process}} | {{see also|0.35 µm process}} | ||
− | StrongARM was manufactured on a [[0.35 µm process]] at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective | + | StrongARM was manufactured on a [[0.35 µm process]] at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective gate length. The CMOS process had 3 metal layers and allowed for a supply voltage of 1.5 V with up to 2 V for highest clocks. |
== Architecture == | == Architecture == | ||
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** L1 Data Cache | ** L1 Data Cache | ||
*** 16 KiB, 32-way set associative | *** 16 KiB, 32-way set associative | ||
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** No L2 cache | ** No L2 cache | ||
* TLB | * TLB | ||
− | + | ** 32-entry, fully associative | |
− | + | ** Each entry can map 4 KiB small pages, 64 KiB large pages, and 1 MiB sections | |
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== Die == | == Die == | ||
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* 49.92 mm² die size | * 49.92 mm² die size | ||
* TQFP-144 package | * TQFP-144 package | ||
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== All StrongARM chips == | == All StrongARM chips == | ||
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== References == | == References == | ||
* Witek, Rich, and James Montanaro. "StrongARM: a high-performance ARM processor." Compcon'96. 'Technologies for the Information Superhighway' Digest of Papers. IEEE, 1996. | * Witek, Rich, and James Montanaro. "StrongARM: a high-performance ARM processor." Compcon'96. 'Technologies for the Information Superhighway' Digest of Papers. IEEE, 1996. | ||
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Facts about "StrongARM - Microarchitectures - DEC"
codename | StrongARM + |
core count | 1 + |
designer | DEC + and ARM Holdings + |
first launched | February 5, 1996 + |
full page name | dec/microarchitectures/strongarm + |
instance of | microarchitecture + |
instruction set architecture | ARMv4 + |
manufacturer | DEC + and Intel + |
microarchitecture type | CPU + |
name | StrongARM + |
pipeline stages | 5 + |
process | 350 nm (0.35 μm, 3.5e-4 mm) + |