Editing cavium/thunderx2/cn9960

{{cavium title|ThunderX2 CN9960}}
{{chip
|name=ThunderX2 CN9960
|no image=Yes
|designer=Cavium
|manufacturer=TSMC
|model number=CN9960
|part number=CN9960-2200LG4077-Y21-G
|part number 2=CN9960-2000LG4077-Y21-G
|part number 3=CN9960-1800LG4077-Y21-G
|part number 4=CN9960-1600LG4077-Y21-G
|market=Server
|first announced=May 7, 2018
|first launched=May 7, 2018
|family=ThunderX2
|frequency=1,600 MHz
|frequency 2=1,800 MHz
|frequency 3=2,000 MHz
|frequency 4=2,200 MHz
|isa=ARMv8.1
|isa family=ARM
|microarch=Vulcan
|process=16 nm
|technology=CMOS
|word size=64 bit
|core count=16
|thread count=64
|max cpus=2
|max memory=2 TiB
|package name 1=cavium,fclga_4077
}}
'''ThunderX2 CN9960''' is a {{arch|64}} [[hexadeca-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9960 operates between 1.6 GHz and 2.2 GHz and supports up to quad-channel DDR4-2666 memory.

== Cache ==
{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
{{cache size
|l1 cache=1 MiB
|l1i cache=512 KiB
|l1i break=16x32 KiB
|l1i desc=8-way set associative
|l1d cache=512 KiB
|l1d break=16x32 KiB
|l1d desc=8-way set associative
|l2 cache=4 MiB
|l2 break=16x256 KiB
|l2 desc=8-way set associative
|l3 cache=16 MiB
|l3 break=16x1 MiB
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=2 TiB
|controllers=2
|channels=4
|max bandwidth=79.47 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=48
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
|pcie config 4=x1
}}
{{expansions entry
|type=SATA
|sata revision=3
|sata ports=2
}}
{{expansions entry
|type=USB
|usb revision=3
|usb ports=2
}}
}}

== Features == 
{{arm features
|thumb=No
|thumb2=No
|thumbee=No
|vfpv1=No
|vfpv2=No
|vfpv3=No
|vfpv3-d16=No
|vfpv3-f16=No
|vfpv4=No
|vfpv4-d16=No
|vfpv5=No
|neon=Yes
|trustzone=Yes
|jazelle=No
|wmmx=No
|wmmx2=No
|pmuv3=Yes
|crc32=Yes
|crypto=Yes
|fp=Yes
|fp16=No
|profile=No
|ras=No
|simd=Yes
|rdm=No
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	ThunderX2 CN9960 - Cavium#pcie +
base frequency	1,600 MHz (1.6 GHz, 1,600,000 kHz) +, 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) +
core count	16 +
designer	Cavium +
family	ThunderX2 +
first announced	May 7, 2018 +
first launched	May 7, 2018 +
full page name	cavium/thunderx2/cn9960 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8.1 +
isa family	ARM +
l1$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldate	May 7, 2018 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
max sata ports	2 +
max usb ports	2 +
microarchitecture	Vulcan +
model number	CN9960 +
name	ThunderX2 CN9960 +
package	FCLGA-4077 +
part number	CN9960-2200LG4077-Y21-G +, CN9960-2000LG4077-Y21-G +, CN9960-1800LG4077-Y21-G + and CN9960-1600LG4077-Y21-G +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2666 +
technology	CMOS +
thread count	64 +
word size	64 bit (8 octets, 16 nibbles) +