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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
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|name=Poseidon
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|name=Ares
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
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|introduction=2021
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|process 2=5 nm
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|process=5 nm
 
 
|oooe=Yes
 
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
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'''Poseidon''' is the successor to {{\\|Zeus}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
'''Poseidon''' is the successor to {{\\|Zeus}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
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== History ==
 
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[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
 
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Poseidon was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
 
  
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== Release Dates ==
 
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Poseidon is expected to show up in products around 2021.
 
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== Process Technology ==
 
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Poseidon specifically designed takes advantage of the power and area advantages of the [[5nm process]].
 
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== Architecture ==
 
 
{{future information}}
 
{{future information}}
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=== Key changes from {{\\|Zeus}} ===
 
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* [[5 nm process]] (from [[7nm]])
 
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{{expand list}}
 
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== Bibliography ==
 
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* Drew Henry keynote, TechCon 2018 keynote.
 

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Facts about "Poseidon - Microarchitectures - ARM"
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codenamePoseidon +
designerARM Holdings +
first launched2021 +
full page namearm holdings/microarchitectures/poseidon +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
namePoseidon +
process5 nm (0.005 μm, 5.0e-6 mm) +