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− | '''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which | + | '''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implemented the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microcontrllers, low-power chips, and in the embedded subsystems of more powerful chips. |
== History == | == History == | ||
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== Process Technology == | == Process Technology == | ||
− | + | Though the Cortex-M55 is designed to be fabricated on various different [[process nodes]] ranging from very mature nodes such as the [[130 nm]] to leading-edge [[7 nm]] and [[5 nm]] nodes. | |
== Compiler support == | == Compiler support == | ||
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== Architecture == | == Architecture == | ||
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=== Block Diagram === | === Block Diagram === | ||
− | :[[File:cortex-m55 block diagram.svg| | + | :[[File:cortex-m55 block diagram.svg|800px]] |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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== Overview == | == Overview == | ||
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The Cortex-M55 is a synthesizable ultra-low-power core designed by [[Arm]] for an array of applications such as microcontrollers and embedded subsystems doing background work on more performant SoCs. Successionally and architecturally, the Cortex-M55 is the successor to the {{\\|Cortex-M7}} and the {{\\|Cortex-M4}}, although in purely raw performance it's slightly behind the M7, though it makes up for it in new technologies such as its {{arm|Helium|new vector extension}}. The Cortex-M55 is said to deliver 1.6 [[Dhrystone DMIPS/MHz]] and 4.2 [[CoreMark/MHz]] which is about 25% higher than the {{\\|Cortex-M4|M4}} but about 20% lower than the {{\\|Cortex-M7|M7}}. In terms of frequency, the M55 is said to deliver up to 15% higher clock speed over the {{\\|Cortex-M4|M4}}. | The Cortex-M55 is a synthesizable ultra-low-power core designed by [[Arm]] for an array of applications such as microcontrollers and embedded subsystems doing background work on more performant SoCs. Successionally and architecturally, the Cortex-M55 is the successor to the {{\\|Cortex-M7}} and the {{\\|Cortex-M4}}, although in purely raw performance it's slightly behind the M7, though it makes up for it in new technologies such as its {{arm|Helium|new vector extension}}. The Cortex-M55 is said to deliver 1.6 [[Dhrystone DMIPS/MHz]] and 4.2 [[CoreMark/MHz]] which is about 25% higher than the {{\\|Cortex-M4|M4}} but about 20% lower than the {{\\|Cortex-M7|M7}}. In terms of frequency, the M55 is said to deliver up to 15% higher clock speed over the {{\\|Cortex-M4|M4}}. | ||
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== Pipeline == | == Pipeline == | ||
The Cortex-M55 is a 4-stage [[in-order]] [[scalar pipeline]] design. The design comprises of the main pipeline which is always present and an extended processing unit. The main pipeline is the typical integer pipeline designed to support the full {{arm|ARMv8.1-M}} ISA. The extended processing unit is optional and is only present when the core implements the FPU or the {{arm|Helium}} extensions. When the extended processing unit is present, that part of the pipeline is extended by an additional stage (for a total of 5 stages). The separate pipeline allows the core to go into retention state or be entirely power-down when not used. | The Cortex-M55 is a 4-stage [[in-order]] [[scalar pipeline]] design. The design comprises of the main pipeline which is always present and an extended processing unit. The main pipeline is the typical integer pipeline designed to support the full {{arm|ARMv8.1-M}} ISA. The extended processing unit is optional and is only present when the core implements the FPU or the {{arm|Helium}} extensions. When the extended processing unit is present, that part of the pipeline is extended by an additional stage (for a total of 5 stages). The separate pipeline allows the core to go into retention state or be entirely power-down when not used. | ||
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=== Fetch & Decode === | === Fetch & Decode === | ||
− | The M55 features a configurable private [[instruction cache]]. It is optional, but when present, it can be configured from 0 KiB to 64 KiB organized as a 2-way set associative. There is also optional ECC support if desired. Each cycle, four bytes are fetched from the instruction cache. There, instructions are pre-parsed and are sent to the decode. Since the {{arm|ARMv8}} supports a limited subset of {{arm|T16}}, when two adjacent instructions are both 16-bit wide | + | The M55 features a configurable private [[instruction cache]]. It is optional, but when present, it can be configured from 0 KiB to 64 KiB organized as a 2-way set associative. There is also optional ECC support if desired. Each cycle, four bytes are fetched from the instruction cache. There, instructions are pre-parsed and are sent to the decode. Since the {{arm|ARMv8}} supports a limited subset of {{arm|T16}}, when two adjacent instructions are both 16-bit wide, the two instructions may be sent to decode to be decoded simultaneously. However, since the dual-issue capabilities are incredibly limited, Arm does not classify the design as a superscalar (unlike the capabilities of the {{\\|Cortex-M7}}). |
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=== Extended processing pipeline === | === Extended processing pipeline === | ||
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The Cortex-M55 features a fairly complex memory subsystem. The two main parts are the [[tightly-coupled memory]] (TCM) and the cache subsystem. Both are optional and both are configurable in sizes. The TCM is optimized for real-time applications with highly deterministic behaviors while the cache subsystem is designed for complex memory hierarchies, hiding higher latencies. The main bus interface to the Cortex-M55 from the rest of the system is the 64-bit [[AMBA 5 AXI]]. The interface supports multiple outstanding memory transfers as well as burst transfers and can operate at the core frequency or at some divided clock frequency. | The Cortex-M55 features a fairly complex memory subsystem. The two main parts are the [[tightly-coupled memory]] (TCM) and the cache subsystem. Both are optional and both are configurable in sizes. The TCM is optimized for real-time applications with highly deterministic behaviors while the cache subsystem is designed for complex memory hierarchies, hiding higher latencies. The main bus interface to the Cortex-M55 from the rest of the system is the 64-bit [[AMBA 5 AXI]]. The interface supports multiple outstanding memory transfers as well as burst transfers and can operate at the core frequency or at some divided clock frequency. | ||
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+ | The TCM subsystem is somewhat similar to the one found in the {{\\|Cortex-M7}} but comes with a few noticeable differences. The TCM consists of an instruction TCM (I-TCM) and a data TCM (D-TCM). The instruction TCM is optional and configurable from 0 to 16 MiB with optional ECC support. It is 32-bit wide, allowing up to 4 bytes per cycle to be transferred from the I-TCM to either the [[instruction fetch]] or the [[instruction memory]]. The D-TCM is also optional and is configurable from 0 to 16 MiB in capacity with optional ECC support. Whereas the {{\\|Cortex-M7}} featured two 32-bit data TCM interfaces, the M55 features four 32-bit data TCM interfaces which are split equally using address bits[3:2]. The data TCM interfaces collectively have an aggregated bandwidth of 128-bit per cycle, however since the Helium vector extension features an interface data path of 64-bit, software execution can only generate 64-bit data transfers per cycle. The rest of the bandwidth can be used for other purposes such as data memory access operations, transferring data from and to the TCM simultaneously while the data is read by the core execution. Accesses to TCM memory banks are prioritized for software execution, therefore an attempt by the DMA controller will be stalled while the software is reading form the same TCM bank. | ||
There are a number of additional interfaces including a 32-bit AHB peripheral interface for legacy AHB peripherals. A debug AHB interface is a 32-bit debug AHB5 slave interface providing debug support for the Debug Access Port (DAP) to the memory system. | There are a number of additional interfaces including a 32-bit AHB peripheral interface for legacy AHB peripherals. A debug AHB interface is a 32-bit debug AHB5 slave interface providing debug support for the Debug Access Port (DAP) to the memory system. | ||
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== All Cortex-M55 chips == | == All Cortex-M55 chips == |
Facts about "Cortex-M55 - Microarchitectures - ARM"
codename | Cortex-M55 + |
core count | 1 +, 2 + and 4 + |
designer | ARM Holdings + |
first launched | February 10, 2020 + |
full page name | arm holdings/microarchitectures/cortex-m55 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.1-M + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-M55 + |
pipeline stages (max) | 5 + |
pipeline stages (min) | 4 + |
process | 55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |