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− | '''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which | + | '''Cortex-M55''' is an ultra-low-power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for microcontrollers and embedded subsystems. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-M55, which implemented the {{arm|ARMv8.1-M}} ISA, is an ultra-low-power core which is often found in microcontrllers, low-power chips, and in the embedded subsystems of more powerful chips. |
== History == | == History == |
Facts about "Cortex-M55 - Microarchitectures - ARM"
codename | Cortex-M55 + |
core count | 1 +, 2 + and 4 + |
designer | ARM Holdings + |
first launched | February 10, 2020 + |
full page name | arm holdings/microarchitectures/cortex-m55 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.1-M + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-M55 + |
pipeline stages (max) | 5 + |
pipeline stages (min) | 4 + |
process | 55 nm (0.055 μm, 5.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |