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|introduction=October 3, 2007 | |introduction=October 3, 2007 | ||
|process=40 nm | |process=40 nm | ||
− | |||
|predecessor=Cortex-A8 | |predecessor=Cortex-A8 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a8 | |predecessor link=arm_holdings/microarchitectures/cortex-a8 | ||
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|successor 4 link=arm_holdings/microarchitectures/cortex-a5 | |successor 4 link=arm_holdings/microarchitectures/cortex-a5 | ||
}} | }} | ||
− | '''Cortex-A9''' | + | '''Cortex-A9''' is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. |
The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}). | The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}). | ||
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|} | |} | ||
− | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because | + | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior. |
== Architecture == | == Architecture == | ||
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* Fully synthesizable RTL (prior designs were hand/automated layout) | * Fully synthesizable RTL (prior designs were hand/automated layout) | ||
* [[40 nm process]] (from [[65 nm]]) | * [[40 nm process]] (from [[65 nm]]) | ||
− | * New [[out-of-order]] pipeline ( | + | * New [[out-of-order]] pipeline (form [[in-order]]) |
** Shorter pipeline (9-12 stages, down from 13) | ** Shorter pipeline (9-12 stages, down from 13) | ||
* 2x frequency (2 GHz, up from 1 GHz) | * 2x frequency (2 GHz, up from 1 GHz) |
Facts about "Cortex-A9 - Microarchitectures - ARM"
codename | Cortex-A9 + |
designer | ARM Holdings + |
first launched | October 3, 2007 + |
full page name | arm holdings/microarchitectures/cortex-a9 + |
instance of | microarchitecture + |
instruction set architecture | ARMv7 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A9 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) + |