Editing amd/microarchitectures/zen

{{amd title|Zen|arch}}
{{microarchitecture
| atype            = CPU
| name             = Zen
| designer         = AMD
| manufacturer     = GlobalFoundries
| manufacturer 2   = 
| introduction     = March 2, 2017
| phase-out        = 
| process          = 14 nm
| cores            = 2
| cores 2          = 4
| cores 3          = 6
| cores 4          = 8

| pipeline         = Yes
| type             = Superscalar
| OoOE             = Yes
| speculative      = Yes
| renaming         = Yes
| isa              = x86-16
| isa 2            = x86-32
| isa 3            = x86-64
| stages           = <!-- ONLY IF FIXED SIZE, otherwise use below for range -->
| stages min       = 7
| stages max       = 19?
| issues           = 4

| inst             = Yes
| feature          = 
| extension        = MOVBE
| extension 2      = MMX
| extension 3      = SSE
| extension 4      = SSE2
| extension 5      = SSE3
| extension 6      = SSSE3
| extension 7      = SSE4.1
| extension 8      = SSE4.2
| extension 9      = POPCNT
| extension 10     = AVX
| extension 11     = AVX2
| extension 12     = AES
| extension 13     = PCLMUL
| extension 14     = RDRND
| extension 15     = F16C
| extension 16     = BMI
| extension 17     = BMI2
| extension 18     = RDSEED
| extension 19     = ADCX
| extension 20     = PREFETCHW
| extension 21     = CLFLUSHOPT
| extension 22     = XSAVE
| extension 23     = SHA
| extension 24     = CLZERO

| cache            = Yes
| l1i              = 64 KiB
| l1i per          = core
| l1i desc         = 4-way set associative
| l1d              = 32 KiB
| l1d per          = core
| l1d desc         = 8-way set associative
| l2               = 512 KiB
| l2 per           = core
| l2 desc          = 8-way set associative
| l3               = 2 MiB
| l3 per           = core
| l3 desc          = Up to 16-way set associative

| core names       = Yes
| core name        = Raven Ridge
| core name 2      = Summit Ridge
| core name 3      = Snowy Owl
| core name 4      = Naples

| succession         = Yes
| predecessor        = Excavator
| predecessor link   = amd/microarchitectures/excavator
| predecessor 2      = Puma
| predecessor 2 link = amd/microarchitectures/puma
| successor          = Zen+
| successor link     = amd/microarchitectures/zen+
}}
'''Zen''' ('''family 17h''') is the [[microarchitecture]] developed by [[AMD]] as a successor to both {{\\|Excavator}} and {{\\|Puma}}. Zen is an entirely new design, built from the ground up for optimal balance of performance and power capable of covering the entire computing spectrum from fanless notebooks to high-performance desktop computers. Zen is set to be released in early-2017. Zen is set to be eventually replaced by {{\\|Zen+}}.

For performance desktop computing, Zen is branded as {{amd|Ryzen 3}}, {{amd|Ryzen 5}}, and {{amd|Ryzen 7}} processors.
== Etymology ==
''Zen'' was picked by Michael Clark, AMD's senior fellow and lead architect. Zen was picked to represent the balance needed between the various competing aspects of a microprocessor - transistor allocation/die size, clock/frequency restriction, power limitations, and new instructions to implement.

== Codenames ==
{{future information}}

[[File:amd-zen-black-logo.png|right|Zen Logo]]
{| class="wikitable"
|-
! Core !! C/T !! Target
|-
| {{amd|Naples|l=core}} || 32/64 || High-end server multiprocessors
|-
| {{amd|Snowy Owl|l=core}} || 16/32 || Mid-range server processors
|-
| {{amd|Summit Ridge|l=core}} || 8/16 || High-end desktops & enthusiasts market
|-
| {{amd|Raven Ridge|l=core}} || 4/8 || Mainstream desktop & mobile processors with GPU
|}

== Brands ==
[[File:amd ryzen black bg logo.png|thumb|right|Ryzen brand logo]]

{| class="wikitable" style="text-align: center;"
|-
! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
|-
! Cores !! Unlocked !! {{x86|AVX2}} !! [[SMT]]  !! {{amd|XFR}} !! [[IGP]]
|-
| {{amd|Ryzen 3}} || Low-end Performance || [[quad-core|Quad]] || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #ffdad6;" | ✘ || style="background-color: #f9dcb3;" | ✔/✘ || style="background-color: #ffdad6;" | ✘
|-
| rowspan="2" | {{amd|Ryzen 5}} || rowspan="2" | Mid-range Performance || [[quad-core|Quad]] || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #f9dcb3;" | ✔/✘ || style="background-color: #ffdad6;" | ✘
|-
| [[hexa-core|Hexa]] || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #f9dcb3;" | ✔/✘ || style="background-color: #ffdad6;" | ✘
|-
| {{amd|Ryzen 7}} || High-end Performance / Enthusiasts || [[octa-core|Octa]] || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #d6ffd8;" | ✔ || style="background-color: #f9dcb3;" | ✔/✘ || style="background-color: #ffdad6;" | ✘
|}

* '''Note:''' While a model has an unlocked multiplier, not all chipsets support overclocking. (see [[#Sockets/Platform|§Sockets]])
* '''Note:''' 'X' models will enjoy "Full XFR" providing an additional +100 MHz when sufficient thermo/electric requirements are met. Non-X models are limited to just +50 MHz.

== Release Dates == 
The first set of processors, as part of the {{amd|Ryzen 7}} family were introduced at an AMD event on February 22 before the Game Developer Conference (GDC). However initial models don't get shipped until March 2. Server processors are set to be released in by the end of Q2, 2017. Mobile processors are expected to be released by the end of 2017.

== Process Technology ==
Zen is planned to be manufactured on [[Global Foundries]]' [[14 nm process]], same one used by [[IBM]] for their {{ibm|POWER9|l=arch}}. AMD's previous microarchitectures were based on [[32 nm|32]] and [[28 nm|28]] nanometer processes. The jump to 14 nm is part of AMD's attempt to remain competitive against Intel (Both {{intel|SkyLake}} and {{intel|Kaby Lake}} are also manufactured on 14 nm although by late 2017 Intel plans on moving on to {{intel|Cannonlake}} and [[10 nm process]]). The move to 14 nm will bring along related benefits of a smaller node such as reduced heat and power consumption for identical designs.

== Compatibility ==
[[Linux]] added initial support for Zen starting with Linux Kernel 4.1. Microsoft will only support Windows 10 for Zen.

{| class="wikitable"
! Vendor !! OS  !! Version !! Notes
|-
| rowspan="3" | Microsoft || rowspan="3" | Windows || style="background-color: #ffdad6;" | Windows 7 || No Support
|-
| style="background-color: #ffdad6;" | Windows 8 || No Support
|-
| style="background-color: #d6ffd8;" | Windows 10 || Support
|- 
| Linux || Linux || style="background-color: #d6ffd8;" | Kernel 4.1 || Initial Support
|}

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[GCC]] || <code>-march=znver1</code> || <code>-mtune=znver1</code>
|-
| [[LLVM]] || <code>-march=znver1</code> || <code>-mtune=znver1</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || ?
|}

== Architecture ==
AMD Zen is an entirely new design from the ground up which introduces considerable amount of improvements and design changes over {{\\|Excavator}}. Zen-based microprocessors will utilize AMD's {{amd|Socket AM4}} unified platform.

=== Key changes from {{\\|Excavator}} ===
* Zen was designed to succeed BOTH {{\\|Excavator}} (High-performance) and {{\\|Puma}} (Low-power) covering the entire range in one architecture
** Cover the entire spectrum from fanless notebooks to high-performance desktops
** More aggressive clock gating with multi-level regions
** Power focus from design, employs low-power design methodologies
*** >15% switching capacitance (C<sub>AC</sub>) improvement
* Utilizes [[14 nm process]] (from [[28 nm]])
* 52% improvement in IPC per core for a single-thread (From Excavator)
* Return to conventional high-performance x86 design
** Traditional design for cores without shared blocks (e.g. shared SIMD units)
** Large beefier core design
* Core engine
** Simultaneous Multithreading (SMT) support, 2 threads/core (see [[#Simultaneous_MultiThreading_.28SMT.29|§ Simultaneous MultiThreading]] for details)
** Branch Predictor
*** Improved branch mispredictions
**** Better branch predicitons with 2 branches per BTB entry
**** Lower miss latency penalty
*** BP is now decoupled from fetch stage
** Large Op cache (2K instructions)
** Wider μop dispatch (6, up from 4)
** Larger instruction scheduler
*** Integer (84, up form 48)
*** Floating Point (96, up form 60)
** Larger retire throughput (8, up from 4)
** Larger Retire Queue (192, up from 128)
*** duplicated for each thread
** Larger Load Queue (72, up from 44)
** Larger Store Queue (44, up from 32)
*** duplicated for each thread
** Quad-issue FPU (up from 3-issue)
** Faster Load to FPU (down to 7, from 9 cycles)
* Cache system
** L1
*** 64 KiB (double from previous capacity of 32 KiB)
*** Write-back L1 cache eviction policy (From write-through)
*** 2x the bandwidth
** L2
*** 2x the bandwidth
*** Faster L2 cache
** Faster L3 cache
** Large Op cache
** Better L1$ and L2$ data prefetcher
** 5x L3 bandwidth
** Move elimination block added
** Page Table Entry (PTE) Coalescing

==== New instructions ====
Zen introduced a number of new [[x86]] instructions:
* <code>{{x86|ADX}}</code> - Multi-Precision Add-Carry Instruction extension
* <code>{{x86|RDSEED}}</code> - Hardware-based RNG
* <code>{{x86|SMAP}}</code> - Supervisor Mode Access Prevention
* <code>{{x86|SHA}}</code> - SHA extensions
* <code>{{x86|CLFLUSHOPT}}</code> - Flush Cache Line
* <code>{{x86|XSAVE}}</code> - Privileged Save/Restore
* <code>{{x86|CLZERO}}</code> - Zero-out Cache Line (AMD exclusive)

While not new, Zen also supports {{x86|AVX}}, {{x86|AVX2}}, {{x86|FMA3}}, {{x86|BMI1}}, {{x86|BMI2}}, {{x86|AES}}, {{x86|RdRand}}, {{x86|SMEP}}. Note that with Zen, AMD dropped support for {{x86|FMA4}}, {{x86|XOP}}, {{x86|TBM}}, and {{x86|LWP}}.

=== Block Diagram ===
==== Individual Core ====
{{future information}}
[[File:zen block diagram.svg]]

=== Memory Hierarchy ===
* Cache
** L1I Cache:
*** 64 KiB 4-way set associative
**** 32 B line size
**** shared by the two threads, per core
** L1D Cache:
*** 32 KiB 8-way set associative
**** 32 B line size
**** write-back policy
*** 4-5 cycles latency for Int
*** 7-8 cycles latency for FP
** L2 Cache:
*** 512 KiB 8-way set associative
*** 32 B line
*** write-back policy
*** 12 cycles latency
** L3 Cache:
*** 2 MiB/core, shared across all cores.
*** Up to 16-way set associative
*** Write-back policy
*** 35 cycles latency
** System DRAM:
*** 2 Channels

Zen TLB consists of dedicated level one TLB for instruction cache and another one for data cache.

* TLBs
** ITLB
*** 8 entry L0 TLB, all page sizes
*** 64 entry L1 TLB, all page sizes
*** 512 entry L2 TLB, no 1G pages
** DTLB
*** 64 entry, all page sizes
** STLB 
*** 1,532-entry data, no 1G pages
*** 512-entry instruction

=== Pipeline ===
[[File:amd zen hc28 page 0004.jpg|525px|right]]
Zen presents a major design departure from the previous couple of [[microarchitecture]]s. In the pursuit of remaining competitive against [[Intel]], AMD went with a similar approach to Intel's: large beefier core with SoC design that can scale from extremely low [[TDP]] ([[fanless]] devices) to [[supercomputers]] utilizing dozens of cores. As such, Zen is aimed at replacing both {{\\|Excavator}} (AMD's previous performance microarchitecture) and {{\\|Puma}} (AMD's previous ultra-low power arch). In addition to covering the entire computing spectrum through power efficiency and [[core]] [[scalability]], another major design goal was 40% uplift in single-thread performance (i.e. 40% IPC increase) from {{\\|Excavator}}. The large increase in performance is the result of major redesigns in all four areas of the core (the front end, the execution engine, and the memory subsystem) as well as Zen's new [[SoC]] CCX (CPU Complex) modular design. The core itself is wider and all around bigger (roughly every component had its capacity substantially increased). The improvement in power efficiency is the result of the [[14 nm process]] used as well as many low-power design methodologies that were utilized early on in the design process (Excavator has been manufactured on [[globalfoundries|GF's]] [[28 nm process]]). AMD introduced various components (such as their new prediction flow and forwarding mechanisms) that eliminate the need for operations to go through the high power ALUs and decoders, increasing the overall power efficiency and throughput.

==== Broad Overview ====
At a very broad view, Zen shares some similarities with its predecessor but introduces new elements and major changes. Each core is composed of a front end ([[in-order]] area) that fetches instructions, decodes them, generates [[µOPs]] and [[fused µOPs]], and sends them to the Execution Engine ([[out-of-order]] section). Instructions are either fetched from the [[L1I$]] or come from the µOPs cache (on subsequent fetches) eliminating the decoding stage altogether. Zen decodes 4 instructions/cycle into the µOP Queue. The µOP Queue dispatches separate µOPs to the Integer side and the FP side (dispatching to both at the same time when possible).

[[File:amd zen hc28 overview.png|350px|left]]

The biggest departure from previous generation is Zen's return to traditional core partitioning - every core is an independent core with its own [[floating-point]]/[[SIMD]] units and a [[L2]] cache. Previously, those units were shared between two cores; they are now once again completely private.

Unlike many of Intel's recent microarchitectures (such as {{intel|Skylake|l=arch}} and {{intel|Kaby Lake|l=arch}}) which make use of a unified scheduler, AMD continue to use a split pipeline design. µOP are decoupled at the µOP Queue and are sent through the two distinct pipelines to either the Integer side or the FP side. The two sections are completely separate, each featuring separate schedulers, queues, and execution units. The Integer side splits up the µOPs via a set of individual schedulers that feed the various ALU units. On the floating point side, there is a different scheduler to handle the 128-bit FP operations. Zen support all modern {{x86|extensions|x86 extensions}} including {{x86|AVX}}/{{x86|AVX2}}, {{x86|BMI1}}/{{x86|BMI2}}, and {{x86|AES}}. Zen also supports {{x86|SHA}}, secure hash implementation instructions that are currently only found in [[Intel]]'s ultra-low power microarchitectures (e.g. {{intel|Goldmont|l=arch}}) but not in their mainstream processors.

From the memory subsystem point of view, data is fed into the execution units from the [[L1D$]] via the load and store queue (both of which were almost doubled in capacity) via the two [[Address Generation Units]] (AGUs) at the rate of 2 loads and 1 store per cycle. Each core also has a 512 KiB level 2 cache. L2 feeds both the the level 1 data and level 1 instruction caches at 32B per cycle (32B can be send in either direction (bidirectional bus) each cycle). L2 is connected to the L3 cache which is shared across all cores. As with the L1 to L2 transfers, the L2 also transfers data to the L3 and vice versa at 32B per cycle (32B in either direction each cycle).

{{clear}}

==== Front End ====
[[File:amd zen hc28 fetch.png|300px|right]]
The Front End of the Zen core deals with the [[in-order]] operations such as [[instruction fetch]] and [[instruction decode]]. The instruction fetch is composed of two paths: a traditional decode path where instructions come from the [[instruction cache]] and a [[µOPs cache]] that are determined by the [[branch prediction]] (BP) unit. The instruction stream and the branch prediction unit track instructions in 64B windows.

The [[branch prediction]] unit is decoupled and can start working as soon as it receives a desired operation such as a redirect, ahead of traditional instruction fetches. AMD still uses a [[perceptron branch predictor|hashed perceptron system]] similar to the one used in {{\\|Jaguar}} and {{\\|Bobcat}}, albeit likely much more finely tuned. AMD stated it's also larger than previous architectures but did not disclose actual sizes. Once the BP detects an indirect target operation, the branch is moved to the Indirect Target Array (ITA) which is 512 entry deep. The BP includes a 32-entry return stack.

In Zen, AMD moved the instruction TLB to BP (to much earlier in the pipeline than in previous architectures). This was done to allow for more-aggressive prefetching by allowing the physical address to be retrieved at an earlier stage. The BP is capable of storing 2 branches per BTB (Branch Target Buffer) entry, reducing the number of BTB reads necessary. ITLB is composed of:

* 8-entry L0 TLB, all page sizes
* 64-entry L1 TLB, all page sizes
* 512-entry L2 TLB, no 1G pages

Instructions are fetched from the [[L2 cache]] at the rate of 32B/cycle. Zen does not have an even [[L1$]]. The [[instruction cache]] is 64 [[KiB]], double that of the data cache. Depending on the branch prediction decision instructions may be fetched from the instruction cache or from the µOPs in which case costly decoding will be avoided.
[[File:amd zen hc28 decode.png|left|300px]]
On the traditional side of decode instructions are fetched from the L1$ at 32B/cycle and go to the instruction byte buffer and through the pick stage to the decode. The size of the instruction byte buffer was not given by AMD but it's expected to be larger than the 16-entry structure found in the previous architecture. The decode allows for four [[x86]] instructions to be decoded per cycle which are in turn sent to the µOP Queue. While up to 8µOPs/cycle can be emitted, usually 4µOPs/cycle are emitted from the Decoder because most instructions map to one µOP. Ideally, most instructions get a hit from the BP and acquire a µOP tag, sending them directly to be retrieved from the µOP cache which are then sent to the µOP Queue. This bypasses most of the expensive fetching and decoding that would otherwise be needed to be done. At this stage of the pipeline, Zen performs additional optimizations such as branch fusion - an operation where a comparison and branch op gets combined into a single µOP (resulting in a single schedule+single execute). 

At the decode stage Zen incorporates the [[microcode]] ROM and the Stack Engine Memfile (SEM). The new Memfile sits between the queue and dispatch monitoring the µOP traffic. The Memfile is capable of performing [[store-to-load forwarding]] right at dispatch for loads that trail behind known stores with physical addresses. Other things such as eliminating stack PUSH/POP operations are also done at this stage. This is a low-power solution that off-loads some of the work that is usually done by the [[AGU]]. 

Dispatch is capable of sending up to 6 µOPs to [[Integer]] EX and an additional 4 µOPs to the [[Floating Point]] (FP) EX. Zen can dispatch to both at the same time (i.e. for a maximum of 10 µOPs per cycle).

{{clear}}

==== Execution Engine ====
[[File:amd zen hc28 integer.png|350px|right]]
As mentioned early, Zen returns to a fully partitioned core design with a private L2 cache and private [[FP]]/[[SIMD]] units. Previously those units were shared resources spanning two cores. Zen's Execution Engine (Back-End) is split into two major sections: [[integer]] & memory operations and [[floating point]] operations. The two sections are decoupled with independent [[schedulers]] and [[queues]]. Both Integer and FP sections have access to the [[Retire Queue]] which is 192 entries and can [[retire]] 8 instructions per cycle (independent of either Integer or FP). The wider-than-dispatch retire allows Zen to catch up and free the resources much quicker (previous architectures saw bottleneck at this point in situations where an older op is stalling causing a reduction in performance due to retire needing to catch up to the front of the machine).

===== Integer =====
The Integer Execute can receive up to 6 µOPs/cycle from Dispatch where it is mapped from [[logical registers]] to [[physical registers]]. Zen has a 168-entry physical integer [[register file]], an identical size to that of {{intel|Broadwell|l=arch}}. Instead of a large scheduler, Zen has 6 distributed scheduling queues, each 14 entries deep (4x[[ALU]], 2x[[AGU]]). Zen includes a number of enhancements such as differential checkpoints tracking branch instructions and eliminating redundant values as well as [[move eliminations]]. Note that register moves are done internally by modifying the register mapping rather than through an execution of a µOP. Zen can work on two branches per cycle in the two ALUs that support that operation. While AMD stated that the ALUs are largely symmetric except for a number of exceptions, it's still unknown which operations are reserved to which units.

===== Floating Point =====
[[File:amd zen hc28 fp.png|350px|left]]
The Floating Point side can receive up to 4 µOPs/cycle from Dispatch where it is mapped from [[logical registers]] to [[physical registers]]. Zen has a 160-entry physical floating point [[register file]] which is 8 entries smaller than the one used in [[Intel]]'s {{intel|Skylake|l=arch}}/{{intel|Kaby Lake|l=arch}} architectures. The register file can perform direct transfers to the Integer register files as needed. Before ops go to the scheduling queue, they go through the Non-Scheduling Queue (NSQ) first which is essentially a wait buffer. Because FP instructions typically have higher latency, they can create a back-up at Dispatch. The non-scheduling queue attempts to reduce this by queuing more FP instructions which lets Dispatch continue on as much as possible on the Integer side. Additionally, the NSQ can go ahead and start working on the memory components of the FP instructions so that they can be ready once they go through the Scheduling Queue. The FP has a single pipe for 128-bit load operations. The FP scheduler has four pipes (1 more than that of {{\\|Excavator}}) and operates on 128-bit floating point. In fact, the entire FP side is optimized for 128-bit operations. Zen supports all the latest instructions such as SSE and {{x86|AVX1}}/{{x86|AVX2|2}}. The various 265-bit AVX1/2 operations are done by working on individual 128-bit chunks at a time and fuse them together - this does mean 256-bit instructions require twice the resources all-around including (i.e., 2x register+scheduler entries). This does put Zen behind Intel's latest architectures which do have dedicated 265-bit circuitry. Additionally Zen also supports {{x86|SHA}} and {{x86|AES}} with 2 AES units implemented in an attempt to improve encryption performance.

{{clear}}

==== Memory Subsystem ====
[[File:amd zen hc28 memory.png|300px|right]]
Loads and Stores are conducted via the two AGUs which can operate simultaneously. Zen has a much larger load queue capable of supporting 72 out-of-order loads (same as Intel's {{intel|Skylake|l=arch}}). There is also a 44-entry Store Queue. Zen employs a split TLB-data pipe design which allows TLB tag access to take place while the data cache is being fed in order to determine if the data is available and send their address to the L2 to start prefetching early on. Zen is capable of up to two loads per cycle (2x16B each) and up to one store per cycle (1x16B). The L1 TLB is 64-entry for all page sizes and the L2 TLB is a 1536-entry with no 1 GiB pages.

Zen incorporates a 64 KiB 4-way set associative L1 instruction cache an a 32 KiB 8-way set associative L2 data cache. Both the instruction cache and the data cache can fetch from the L2 cache at 32 Bytes per cycle. The L2 cache is a 512 KiB 8-way set associative unified cache, inclusive, and private to the code. The L2 cache can fetch and write 32B/cycle into the L3 (32B in either direction each cycle, i.e. bidirectional bus).

== Features ==
AMD introduced a series of new features in their new Zen microarchitecture:

=== Simultaneous MultiThreading (SMT) ===
Perhaps the single biggest enhancement to Zen is the addition of full-fledged [[simultaneous multithreading]] (SMT) support (a technology similar to {{intel|Hyper-Threading}} found in Intel processors). This is a departure from AMD's previous lightweight (and largely ineffective and to some degree misleading) {{amd|Clustered Multithreading}} (CMT). Zen is a properly simultaneous multi-threaded machine capable of handling two threads of execution throughout the entire machine. Below is a breakdown of how the various core components work under SMT:

[[File:amd zen hc28 smt.png|400px|left]]

* <span style="background-color: #ef6e71;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span> - Competitively shared structures
* <span style="background-color: #62d7de;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span> - Competitively shared and SMT tagged
* <span style="background-color: #6f8ee7;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span> - Competitively shared with Algorithmic Priority
* <span style="background-color: #c1e169;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span> - Statically Partitioned

The basics behind SMT are always the same: high utilization of resources through multiple [[threads]] of execution. When a single thread is running all structures become fully available to that thread as needed. With the introduction of SMT and a second thread, Zen attempts to share as much of the resources as possible in an attempt to balance out the throughput and deliver the appropriate structures to each thread as the software requires. The various structures can dynamically shift their resources depending on the kind of workload being executed. Structures that are competitively shared by the two threads (shaded in red in the diagram) include the execution units, [[schedulers]], [[register file]], the decode, and cache (including the µOP cache). The load queue, [[ITLB]], and [[DTLB]] (shaded in dark cyan) are also competitively shared but require SMT tagging - resources (i.e. entries capacity) are shared between the threads but actual entry values (e.g. addresses) can only be accessed by the owning thread.

The [[branch predictor]] and the two register renaming/allocation units (shaded in blue) are competitively shared with algorithmic priority. Zen provides additional logic to give a certain thread temporary priority in resource allocation over the other thread. One such occasion is when the BP encounters a flush on one of the threads. Temporary priority is given to that thread in order to help it fetch much instructions as it could so it can get going again. Additionally, similar logic can be found at dispatch to ensure good throughput by both threads and high utilization of the execution units.

The µOP Queue, Retire Queue, and Store Queue (shaded in green on the diagram) are statically partitioned, i.e. those units have duplicate logic to handle each thread independently. Those were duplicated instead of shared simply due to the high complexity involved in doing so.

{{clear}}

=== SenseMI Technology ===
'''SenseMI Technology''' (pronounced ''Sense-Em-Eye'') is an umbrella term for a number of features AMD added to Zen microprocessors designed to increase performance through various ways:

[[File:10682-icon-neural-net-prediction-140x140.png|50px|left]]
'''Neural Net Prediction''' - This appears to be largely marketing term for Zen's much beefier and more finely tune [[branch prediction]] unit. Zen uses a [[perceptron branch predictor|hashed perceptron system]] to intelligently anticipate future code flows, allowing warming up of cold blocks in order to avoid possible waits. Most of that functionality is already found on every modern high-end microprocessor (including AMD's own previous microarchitectures). Because AMD has not disclosed any more specific information about BP, it can only be speculated that no new groundbreaking logic was introduced in Zen.
{{clear}}
[[File:10682-icon-smart-prefetch-140x140.png|50px|left]]
'''Smart Prefetch''' - As with the Prediction Unit, this too appears to be a marketing term for the number of changes AMD introduced in the fetch stage where the the branch predictor can get a hit on the next µOP and retrieve it via the µOPs cache directly to the µOPs Queue, eliminating the costly decode pipeline stages.
{{clear}}
[[File:10682-icon-pure-power-140x140.png|50px|left]]
'''Pure Power''' - A feature in Zen that allows for [[dynamic voltage and frequency scaling]] (DVFS), similar to AMD's {{amd|PowerTune}} technology, along with a number of other enhancements that extends beyond the core to the Infinity Fabric (AMD's new proprietary interconnect). Pure Power monitors the temperature, frequency, and voltage of the chip which in term gets used by ''Precision Boost'' and ''Extended Frequency Range'' 
{{clear}}
[[File:10682-icon-precision-boost-140x140.png|50px|left]]
'''Precision Boost''' - A feature that provides the ability to adjust the frequency of the processor on-the-fly given sufficient headroom (e.g. thermal limits based on the sensory data collected by Pure Power), i.e. "Turbo Frequency". Precision Boost adjusts in 25 MHz increments, considerably more granular when compared to Intel's {{intel|Turbo Boost}} which operates at 100 MHz bin increments.
{{clear}}
[[File:amd zen xfr.jpg|300px|right]]
[[File:10682-icon-frequency-range-140x140.png|50px|left]]
'''Extended Frequency Range''' ('''XFR''') - This is a fully automated solution that attempts to allow higher upper limit on the maximum frequency based on the cooling technique used (e.g. air, water, LN2). Whenever the chip senses that it's suitable enough for a given frequency, it will attempt to increase that limit further. XFR is partially enabled on all models, providing an extra +50 MHz frequency boost whenever possible. For 'X' models, full XFR is enabled providing twice the headroom of up to +100 MHz.
{{clear}}


[[File:ryzen-xfr-1800x example.jpg|right|500px]]
The AMD presentation slide on the right depicts a normal use case for the {{amd|Ryzen 7}} {{amd|Ryzen 7/1800X|1800X}}. When under normal workload, the processor will operate at around its base frequency of 3.6 GHz. When expericing havier workload, Precision Boost will kick in increment it as necessary up to its maximum frequency of 4 GHz. With adequate cooling, {{amd|XFR}} will bump it up an additional 100 MHz. When light workload get experienced, the processor will reduce its frequency. A Pure Power senses the workload and CPU state, it can also drastically downclock the CPU when appropriate (such as in the graph during mostly idle).
{{clear}}

== Scalability ==
=== CPU Complex (CCX) ===
AMD organized Zen in groups of cores called a '''CPU Complex''' ('''CCX'''). Each CCX consists of four cores connected to an L3 cache. The L3 cache is an 8 MiB 16-way set associative and is mostly exclusive of the L2. The L3 cache is made of four slices (providing 2 MiB L3 slice/core) organized by low-order address interleaved. Every core can access every L3 cache slice with the same average latency.

Depending on the exactly processor model, an 8-core processor will incorporate two CPU Complexes. It's important to note that the L3 in Zen is not a true last level cache (LLC) as the 16 MiB L3$ will consist of two separate 8 MiB and not one unified L3. While no details have yet been disclosed, AMD did state that the separate complexes can communicate with each other via their custom fabric which connects the CCXs along with the memory controller and I/O. 

<div style="display: inline-block">
<div style="float: left; margin: 10px;">[[File:zen ccx.svg|400px]]</div>
<div style="float: left; margin: 10px;">[[File:amd zen ccx.png]]</div></div>
{{clear}}


[[File:zen ccx voltage.png|left|250px]]

* '''RDL''' - Redistribution layer
* '''LDOs''' - Regulate RVDD to create VDD per core
* '''RVDD''' - Ungated supply
* '''VDD''' - Gated core supply
* '''VDDM''' - [[L2]]/[[L3]] [[SRAM]] supply

{{clear}}

== Die ==
=== Core ===
Fabricated on a [[14 nm process]], using 12 metal layers.

<div style="display: inline-block;">
<div style="float: left; margin: 10px;">
'''Core'''
* Area 7 mm²
* L2 512 KiB; 1.5 mm²/core
[[File:amd zen core die.png|400px]]
</div>
<div style="float: left;  margin: 10px;">
'''CCX'''
* Area 44 mm²
* L3 8 MiB; 16 mm²
* 1,400,000,000 transistors
[[File:amd zen ccx.png|450px]]
</div>
</div>

=== Octa-Core Die ===
* [[14 nm process]]
* 12 metal layers
* 2,000 meters of signals
* 4,800,000,000 transistors
* ~195 mm²

[[File:amd zen octa-core die shot.png|950px]]

== Sockets/Platform ==
All Zen-based microprocessors utilizes AMD's {{amd|Socket AM4}}, a unified socket infrastructure.

{{amd socket am4 chipsets}}

== All Zen Chips ==

<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of all Zen-based Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="14">Processor</th><th colspan="3">Features</th></tr>
{{comp table header 1|cols=Price, Process, Launched, Family, Core, C, T, L3$, L2$, L1$, Freq, Turbo, TDP, Max Mem, SMT, AMD-V, XFR}}
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen]]
 |?full page name
 |?model number
 |?release price
 |?process
 |?first launched
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?l3$ size
 |?l2$ size
 |?l1$ size#KiB
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |?max memory#GiB
 |?has simultaneous multithreading
 |?has amd amd-vi technology
 |?has amd extended frequency range
 |format=template
 |template=proc table 3
 |userparam=19:17
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen]]}}
</table>
{{comp table end}}

== Shop ==
<amazon type="simple-listing1" search-title="AMD Zen Products" search-phrase="AMD Ryzen" />

== References ==
* Michael Clark, AMD's senior fellow and lead architect, Hot Chips 28
* Lisa Su, AMD CEO, AMD: New Horizon Live Event
* Lisa Su, AMD CEO, AMD Annual Meeting of Shareholders Q4 2016
* Meet the AMD Experts - AMD Monthly Partner Training, January 2017
* Zen: A Next-Generation High-Performance x86 Core, ISSCC 2017

== See also ==
* {{intel|Kaby Lake}}
* {{intel|Cannonlake}}
codename	Zen +
core count	4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 +
designer	AMD +
first launched	March 2, 2017 +
full page name	amd/microarchitectures/zen +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	GlobalFoundries +
microarchitecture type	CPU +
name	Zen +
pipeline stages	19 +
process	14 nm (0.014 μm, 1.4e-5 mm) +