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Latest revision | Your text | ||
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|introduction=April 13, 2018 | |introduction=April 13, 2018 | ||
|process=12 nm | |process=12 nm | ||
− | |cores= | + | |cores=2 |
|cores 2=4 | |cores 2=4 | ||
|cores 3=6 | |cores 3=6 | ||
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|cores 5=12 | |cores 5=12 | ||
|cores 6=16 | |cores 6=16 | ||
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− | |||
|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
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|l3 per=core | |l3 per=core | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
− | |core name | + | |core name=Pinnacle Ridge |
− | + | |core name 2=Colfax | |
− | |core name | ||
|predecessor=Zen | |predecessor=Zen | ||
|predecessor link=amd/microarchitectures/zen | |predecessor link=amd/microarchitectures/zen | ||
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|succession=Yes | |succession=Yes | ||
}} | }} | ||
− | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ | + | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ is expected to be replaced by {{\\|Zen 2}} in 2019. |
− | Zen+ based processors are sold under the brand | + | Zen+ based processors are sold under the brand {{amd|Ryzen}} 2nd Generation. |
== History == | == History == | ||
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|- | |- | ||
| {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | | {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | ||
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|} | |} | ||
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|- | |- | ||
| colspan="4" | Family 23 Model 8 | | colspan="4" | Family 23 Model 8 | ||
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− | |||
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|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | AMD launched 2nd generation {{amd|Ryzen}} on the 19th April of 2018. 2nd Generation {{amd|Ryzen Threadripper}} | + | AMD launched 2nd generation {{amd|Ryzen}} on the 19th April of 2018. 2nd Generation {{amd|Ryzen Threadripper}} and Ryzen PRO processors will launch in the second half of 2018. |
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* [[12 nm process]] (from [[14 nm]]) | * [[12 nm process]] (from [[14 nm]]) | ||
* {{amd|Precision Boost 2}} (from Precision Boost) | * {{amd|Precision Boost 2}} (from Precision Boost) | ||
− | ** | + | ** Uses linear model based on temp/current/voltage feedbacks (From 2-core/all-core boost model) |
* {{amd|XFR 2}} (from XFR 1) | * {{amd|XFR 2}} (from XFR 1) | ||
* Cache | * Cache | ||
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*** Bug fixes | *** Bug fixes | ||
*** OEM related issues resolved (unspecified) | *** OEM related issues resolved (unspecified) | ||
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− | |||
=== Block Diagram === | === Block Diagram === | ||
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=== Memory Subsystem === | === Memory Subsystem === | ||
− | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all | + | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all access patterns. Only mainstream Zen-based {{amd|Ryzen}} processors (i.e., {{amd|Summit Ridge|l=core}}) have a latency of 17 cycles. The problem has been sorted out with Zen+. |
== Die == | == Die == | ||
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|?l3$ size | |?l3$ size | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|?tdp | |?tdp | ||
|format=template | |format=template | ||
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{{comp table end}} | {{comp table end}} | ||
− | == | + | == References == |
* AMD CES Tech Day 2018, Jim Anderson | * AMD CES Tech Day 2018, Jim Anderson | ||
* AMD CES Tech Day 2018, Lisa Su | * AMD CES Tech Day 2018, Lisa Su | ||
* AMD CES Tech Day 2018, Mark Papermaster | * AMD CES Tech Day 2018, Mark Papermaster | ||
− | |||
== Documents == | == Documents == |
Facts about "Zen+ - Microarchitectures - AMD"
codename | Zen+ + |
core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 1 + |
designer | AMD + |
first launched | April 13, 2018 + |
full page name | amd/microarchitectures/zen+ + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen+ + |
pipeline stages | 19 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |