From WikiChip
Editing amd/microarchitectures/zen+
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 7: | Line 7: | ||
|introduction=April 13, 2018 | |introduction=April 13, 2018 | ||
|process=12 nm | |process=12 nm | ||
− | |cores= | + | |cores=2 |
|cores 2=4 | |cores 2=4 | ||
|cores 3=6 | |cores 3=6 | ||
Line 13: | Line 13: | ||
|cores 5=12 | |cores 5=12 | ||
|cores 6=16 | |cores 6=16 | ||
− | |||
− | |||
|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
Line 58: | Line 56: | ||
|l3 per=core | |l3 per=core | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
− | |||
− | |||
− | |||
|predecessor=Zen | |predecessor=Zen | ||
|predecessor link=amd/microarchitectures/zen | |predecessor link=amd/microarchitectures/zen | ||
Line 67: | Line 62: | ||
|succession=Yes | |succession=Yes | ||
}} | }} | ||
− | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ | + | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ is expected to be replaced by {{\\|Zen 2}} in 2019. |
− | Zen+ based processors are sold under the brand | + | Zen+ based processors are sold under the brand {{amd|Ryzen}} 2nd Generation. |
== History == | == History == | ||
− | [[File:amd zen+ roadmap.png|right| | + | [[File:amd zen+ roadmap.png|right|500px]] |
− | Zen+ | + | Zen+ is set to succeed {{\\|Zen}} in April of 2018. Zen+ will feature the same core as Zen but will take advantage of the new [[GlobalFoundries]]' 12nm process to deliver higher clock speeds and improved power consumption. Zen+ was initially mentioned by AMD's senior fellow and lead architect of Zen, Michael Clark, during Hot Chips 28 in [[2016]] as part of AMD's continuing commitment in the high-performance computing market. |
== Codenames == | == Codenames == | ||
+ | {{future information}} | ||
+ | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
! Core !! C/T !! Target | ! Core !! C/T !! Target | ||
− | |||
− | |||
|- | |- | ||
| {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | | {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | ||
− | |||
− | |||
|} | |} | ||
== Process Technology == | == Process Technology == | ||
{{see also|12 nm process}} | {{see also|12 nm process}} | ||
− | Zen | + | Zen is manufactured on [[Global Foundries]]' [[12 nm process]] Leading-Performance (12LP), an enhanced version of their 14nm process. The enhanced process is set to provide as much as 15% higher density and 10% higher performance. 12LP brings around a 10% frequency bump for the {{amd|Ryzen}} lineup at the same power envelopes. |
− | |||
− | |||
== Compatibility == | == Compatibility == | ||
Line 131: | Line 122: | ||
|- | |- | ||
| colspan="4" | Family 23 Model 8 | | colspan="4" | Family 23 Model 8 | ||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | AMD | + | AMD intends on launching 2nd generation {{amd|Ryzen}} in April of 2018. 2nd Generation {{amd|Ryzen Threadripper}} and Ryzen PRO processors will launch in the second half of 2018. |
Line 152: | Line 139: | ||
* [[12 nm process]] (from [[14 nm]]) | * [[12 nm process]] (from [[14 nm]]) | ||
* {{amd|Precision Boost 2}} (from Precision Boost) | * {{amd|Precision Boost 2}} (from Precision Boost) | ||
− | ** | + | ** Uses linear model based on temp/current/voltage feedbacks (From 2-core/all-core boost model) |
* {{amd|XFR 2}} (from XFR 1) | * {{amd|XFR 2}} (from XFR 1) | ||
* Cache | * Cache | ||
Line 165: | Line 152: | ||
*** Bug fixes | *** Bug fixes | ||
*** OEM related issues resolved (unspecified) | *** OEM related issues resolved (unspecified) | ||
− | |||
− | |||
=== Block Diagram === | === Block Diagram === | ||
Line 232: | Line 217: | ||
=== Memory Subsystem === | === Memory Subsystem === | ||
− | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all | + | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all patterns. Only mainstream Zen-based {{amd|Ryzen}} processors (i.e., {{amd|Summit Ridge|l=core}}) have a latency of 17 cycles. The problem has been sorted out with Zen+. |
== Die == | == Die == | ||
=== Zeppelin === | === Zeppelin === | ||
* [[12 nm process]] | * [[12 nm process]] | ||
− | |||
− | |||
− | |||
− | |||
:[[File:amd zen+ zeppelin die shot.png|950px]] | :[[File:amd zen+ zeppelin die shot.png|950px]] | ||
Line 277: | Line 258: | ||
|?l3$ size | |?l3$ size | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|?tdp | |?tdp | ||
|format=template | |format=template | ||
Line 288: | Line 269: | ||
{{comp table end}} | {{comp table end}} | ||
− | == | + | == References == |
* AMD CES Tech Day 2018, Jim Anderson | * AMD CES Tech Day 2018, Jim Anderson | ||
* AMD CES Tech Day 2018, Lisa Su | * AMD CES Tech Day 2018, Lisa Su | ||
* AMD CES Tech Day 2018, Mark Papermaster | * AMD CES Tech Day 2018, Mark Papermaster | ||
− | |||
== Documents == | == Documents == |
Facts about "Zen+ - Microarchitectures - AMD"
codename | Zen+ + |
core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 1 + |
designer | AMD + |
first launched | April 13, 2018 + |
full page name | amd/microarchitectures/zen+ + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen+ + |
pipeline stages | 19 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |