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|introduction=April 13, 2018 | |introduction=April 13, 2018 | ||
|process=12 nm | |process=12 nm | ||
− | |cores= | + | |cores=2 |
|cores 2=4 | |cores 2=4 | ||
|cores 3=6 | |cores 3=6 | ||
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|cores 5=12 | |cores 5=12 | ||
|cores 6=16 | |cores 6=16 | ||
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|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
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|l3 per=core | |l3 per=core | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
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|predecessor=Zen | |predecessor=Zen | ||
|predecessor link=amd/microarchitectures/zen | |predecessor link=amd/microarchitectures/zen | ||
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|succession=Yes | |succession=Yes | ||
}} | }} | ||
− | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ | + | '''Zen+''' (Zen Plus) is the successor to {{\\|Zen}}, a [[12 nm]] [[microarchitecture]] designed by [[AMD]] and introduced in [[2018]] for the mainstream PC, enthusiast, and server markets. Zen+ is expected to be replaced by {{\\|Zen 2}} in 2019. |
− | Zen+ based processors are sold under the brand | + | Zen+ based processors are sold under the brand {{amd|Ryzen}} 2nd Generation. |
== History == | == History == | ||
− | [[File:amd zen+ roadmap.png|right| | + | [[File:amd zen+ roadmap.png|right|500px]] |
− | Zen+ | + | Zen+ is set to succeed {{\\|Zen}} in April of 2018. Zen+ will feature the same core as Zen but will take advantage of the new [[GlobalFoundries]]' 12nm process to deliver higher clock speeds and improved power consumption. Zen+ was initially mentioned by AMD's senior fellow and lead architect of Zen, Michael Clark, during Hot Chips 28 in [[2016]] as part of AMD's continuing commitment in the high-performance computing market. |
== Codenames == | == Codenames == | ||
+ | {{future information}} | ||
+ | |||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
! Core !! C/T !! Target | ! Core !! C/T !! Target | ||
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|- | |- | ||
| {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | | {{amd|Pinnacle Ridge|l=core}} || Up to 8/16 || Mainstream to high-end desktops & enthusiasts market processors | ||
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|} | |} | ||
== Process Technology == | == Process Technology == | ||
{{see also|12 nm process}} | {{see also|12 nm process}} | ||
− | Zen | + | Zen is manufactured on [[Global Foundries]]' [[12 nm process]] Leading-Performance (12LP), an enhanced version of their 14nm process. The enhanced process is set to provide as much as 15% higher density and 10% higher performance. 12LP brings around a 10% frequency bump for the {{amd|Ryzen}} lineup at the same power envelopes. |
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== Compatibility == | == Compatibility == | ||
− | [[Linux]] added initial support for Zen starting with Linux Kernel 4.10. [[Microsoft]] | + | [[Linux]] added initial support for Zen starting with Linux Kernel 4.10. [[Microsoft]] will only support Windows 10 for Zen. |
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{| class="wikitable" | {| class="wikitable" | ||
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|- | |- | ||
| colspan="4" | Family 23 Model 8 | | colspan="4" | Family 23 Model 8 | ||
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|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | AMD | + | AMD intends on launching 2nd generation {{amd|Ryzen}} in April of 2018. 2nd Generation {{amd|Ryzen Threadripper}} and Ryzen PRO processors will launch in the second half of 2018. |
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=== Key changes from {{\\|Zen}} === | === Key changes from {{\\|Zen}} === | ||
* ~10% higher [[clock]] frequency | * ~10% higher [[clock]] frequency | ||
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* [[12 nm process]] (from [[14 nm]]) | * [[12 nm process]] (from [[14 nm]]) | ||
* {{amd|Precision Boost 2}} (from Precision Boost) | * {{amd|Precision Boost 2}} (from Precision Boost) | ||
− | |||
* {{amd|XFR 2}} (from XFR 1) | * {{amd|XFR 2}} (from XFR 1) | ||
* Cache | * Cache | ||
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* Mainstream chipsets (See [[#Sockets/Platform|§ Sockets/Platform]]) | * Mainstream chipsets (See [[#Sockets/Platform|§ Sockets/Platform]]) | ||
** X370 → X470 | ** X370 → X470 | ||
− | *** New StoreMI | + | *** New StoreMI |
*** Lower Power | *** Lower Power | ||
*** Bug fixes | *** Bug fixes | ||
*** OEM related issues resolved (unspecified) | *** OEM related issues resolved (unspecified) | ||
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=== Block Diagram === | === Block Diagram === | ||
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=== Memory Subsystem === | === Memory Subsystem === | ||
− | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all | + | When AMD presented their paper at ISSCC 2018, WikiChip was able to confirm with AMD's SoC architect that {{\\|Zen|Zen's}} L2 latency was always designed to be 12 cycles. In fact all Zen-based microprocessors (including {{amd|EPYC}}, {{amd|Ryzen Threadripper}}, and Zen-based APUs) have an L2 latency of 12 cycles for all patterns. Only mainstream Zen-based {{amd|Ryzen}} processors (i.e., {{amd|Summit Ridge|l=core}}) have a latency of 17 cycles. The problem has been sorted out with Zen+. |
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== Sockets/Platform == | == Sockets/Platform == | ||
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=== StoreMI === | === StoreMI === | ||
[[File:amd 400 series storemi logo.png|left|200px]] | [[File:amd 400 series storemi logo.png|left|200px]] | ||
− | A new feature AMD has added to the 400-series chipset is "{{amd|StoreMI}}", a technology with very similar capabilities to Intel's {{intel|Smart Response Technology}} which attempts to combine the benefits of fast, but expensive, [[solid-state drive|SSDs]] along with cheap high-capacity, but slow, [[hard disk drive|HDDs]]. StoreMI combines the two storage devices into a single virtual drive ( | + | A new feature AMD has added to the 400-series chipset is "{{amd|StoreMI}}", a technology with very similar capabilities to Intel's {{intel|Smart Response Technology}} which attempts to combine the benefits of fast, but expensive, [[solid-state drive|SSDs]] along with cheap high-capacity, but slow, [[hard disk drive|HDDs]]. StoreMI combines the two storage devices into a single virtual drive (since letter drive on {{microsoft|Windows}} and automatically manages and moves the data across the drives. Essentially, the chipset uses the SSD as a cache for traditional hard drives. The idea is to keep the most recent and most accessed data on the SSD in order to improve real-world responsiveness while keeping the less used data in the slower mechanical hard disk in order to preserve the capacity of the SSD. It’s worth noting that this hierarchy of secondary storage devices can actually extend to main memory. Up to 2 GiB of RAM may be configured and reserved as another level of cache for the HDD on top of the SSD. |
== All Zen+ Chips == | == All Zen+ Chips == | ||
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|?l3$ size | |?l3$ size | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|?tdp | |?tdp | ||
|format=template | |format=template | ||
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{{comp table end}} | {{comp table end}} | ||
− | == | + | == References == |
* AMD CES Tech Day 2018, Jim Anderson | * AMD CES Tech Day 2018, Jim Anderson | ||
* AMD CES Tech Day 2018, Lisa Su | * AMD CES Tech Day 2018, Lisa Su | ||
* AMD CES Tech Day 2018, Mark Papermaster | * AMD CES Tech Day 2018, Mark Papermaster | ||
− | |||
== Documents == | == Documents == |
Facts about "Zen+ - Microarchitectures - AMD"
codename | Zen+ + |
core count | 4 +, 6 +, 8 +, 12 +, 16 +, 24 +, 32 + and 1 + |
designer | AMD + |
first launched | April 13, 2018 + |
full page name | amd/microarchitectures/zen+ + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen+ + |
pipeline stages | 19 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |