Editing amd/microarchitectures/k9

{{amd title|K9|arch}}
{{microarchitecture
| atype            = CPU
| name             = K9
| designer         = AMD
| manufacturer     = AMD
| introduction     = 
| phase-out        = 
| process          = 65 nm

| succession       = Yes
| predecessor      = K8
| predecessor link = amd/microarchitectures/k8
| successor        = K10
| successor link   = amd/microarchitectures/k10
}}
'''K9''' was a planned  [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. AMD intended to bring massive parallelism to K9. The microarchitecture was reportedly scrapped after 6 months worth of work. The intended features and the exact reasons AMD cancelled K9 remain unknown.
@@ Line 8: / Line 8: @@
 | phase-out        =
 | process          = 65 nm
-|isa=x86-64
 | succession       = Yes
@@ Line 16: / Line 15: @@
 | successor link   = amd/microarchitectures/k10
 }}
-'''K9''' was a planned  [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. The K9 codename might cover multiple projects at AMD. A deep pipeline design led by Mitch Alsup as Chief Architect, another one intended to bring massive parallelism<ref>Anand Lal Shimpi, [https://www.anandtech.com/show/2229/5 Why is Barcelona late? - AMD - The Road Ahead], anandtech.com. Retrieved on December 1, 2018</ref> and finally, using K9 as a codename for dual-core {{\\|K8}}.
+'''K9''' was a planned  [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. AMD intended to bring massive parallelism to K9. The microarchitecture was reportedly scrapped after 6 months worth of work. The intended features and the exact reasons AMD cancelled K9 remain unknown.
-The whole set of intended features and the exact reasons AMD cancelled K9 remain unknown.
-== Deep pipeline design ==
-The design was led by Mitch Alsup as Chief Architect and attempted to directly compete with [[Intel]] [[netburst|NetBurst]]. It featured a deep pipeline and an advanced trace cache.
-According to Alsup, it was designed to be close to 95% of original {{\\|K8}} IPC but reach 5GHz frequency in a 35 nm process. At the time of cancellation most of the logic was running in SPICE at 5GHz and majority of the layout was done.
-The K9 pipeline was dual-quad issue. It was described by Alsup as: "K9 fetched 8 instructions every other cycle and made 2 branch predictions associated with 3 next fetch addresses every other cycle. K9 issued 4 instructions per cycle and took 2 cycles to issue a fetch width."
-Reportedly, the design was cancelled due to leakage current problems amplified by necessity to embrace the multi-core era. K9's DDR2 SDRAM controller was later used in {{\\|K8}} Rev F and its northbridge technology got put in {{\\|K8}} Rev G.
-== References ==
codename	K9 +
designer	AMD +
full page name	amd/microarchitectures/k9 +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	AMD +
microarchitecture type	CPU +
name	K9 +
process	65 nm (0.065 μm, 6.5e-5 mm) +