Editing amd/epyc/9654p

{{amd title|EPYC 9654P}}
{{chip
|name=EPYC 9654P
|no image=Yes
|designer=AMD
|manufacturer=TSMC
|model number=9654P
|part number=100-100000803
|part number 2=100-100000803WOF
|market=Server
|first announced=
|first launched=November 10, 2022
|release price (tray)=$10625.00
|family=EPYC
|series=9004
|locked=Yes
|frequency=2,400 MHz
|turbo frequency=3,550 MHz
|turbo frequency1=3,700 MHz
|clock multiplier=24
|isa=x86-64
|isa family=x86
|microarch=Zen 4
|core name=Genoa
|core family=25
|core model=17
|core stepping=B1
|cpuid = 0x00A10F11
|process=5 nm
|process 2=6 nm
|technology=CMOS
|mcp=Yes
|die count=13
|word size=64 bit
|core count=96
|thread count=192
|max cpus=1
|max memory=6 TiB
|tdp=360 W
|ctdp down=320 W
|ctdp up=400 W
|package name 1=amd,socket_sp5
}}
'''EPYC 9654P''' is a {{arch|64}} [[96-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in late [[2022]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 4|Zen 4 microarchitecture|l=arch}}, incorporates twelve Core Complex Dies fabricated on a [[TSMC]] [[5 nm process]] and a large I/O die also manufactured by TSMC. The 9654P has a TDP of 360 W with a base frequency of 2.4 GHz and a {{amd|precision boost|boost}} frequency of up to 3.7 GHz. This processor supports up to 6 TiB of 12 channel DDR5-4800 memory per socket. 

== Cache ==
{{main|amd/microarchitectures/zen 4#Memory_Hierarchy|l1=Zen 4 § Cache}}
{{cache size
|l1 cache=6 MiB
|l1i cache=3 MiB
|l1i break=96 × 32 KiB
|l1i desc=8-way set associative
|l1d cache=3 MiB
|l1d break=96 × 32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=96 MiB
|l2 break=96 × 1 MiB
|l2 desc=8-way set associative
|l2 policy=write-back
|l3 cache=384 MiB
|l3 break=12 × 32 MiB
|l3 desc=16-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{main|amd/cores/genoa#Memory Interface|l1=Genoa § Memory Interface}}
{{memory controller
|type=DDR5-4800
|ecc=Yes
|max mem=6 TiB
|controllers=24
|channels=12
|max bandwidth=460.8 GB/s
|bandwidth schan=38.4 GB/s
|bandwidth dchan=76.8 GB/s
|bandwidth qchan=153.6 GB/s
|bandwidth hchan=230.4 GB/s
|bandwidth ochan=307.2 GB/s
|bandwidth dechan=384.0 GB/s
}}

Note one memory channel comprises two independent DDR5 subchannels with 32 data and 8 ECC lanes each.

== Expansions ==
{{main|amd/cores/genoa#Input/Output Interfaces|l1=Genoa § I/O Interfaces}}
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=5.0
|pcie lanes=128
}}
{{expansions entry
|type=SATA
|sata revision=3.0
|sata ports=32
}}
{{expansions entry
|type=USB
|usb revision=3.2 Gen1×1
|usb ports=4
}}
}}

{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=Yes
|sse_gfni=Yes
|avx=Yes
|avx_gfni=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=Yes
|avx512vbmi=Yes
|avx5124fmaps=No
|avx512vnni=Yes
|avx5124vnniw=No
|avx512vpopcntdq=Yes
|avx512gfni=Yes
|avx512vaes=Yes
|avx512vbmi2=Yes
|avx512bitalg=Yes
|avx512vpclmulqdq=Yes
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=Yes
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=Yes
|tbt1=No
|tbt2=No
|tbmt3=No
|tvb=No
|bpt=No
|eist=No
|sst=No
|flex=No
|fastmem=No
|ivmd=No
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=No
|txt=No
|ht=No
|vpro=No
|vtx=No
|vtd=No
|ept=No
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|dlboost=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=Yes
|amdv=Yes
|amdsme=Yes
|amdtsme=Yes
|amdsev=Yes
|rvi=
|smt=Yes
|sensemi=Yes
|xfr=
|xfr2=
|mxfr=
|amdpb=
|amdpb2=
|amdpbod=
}}

== Bibliography ==
* [https://www.amd.com/en/products/specifications "AMD Processor Specifications"]. AMD.com. Retrieved February 2023.
* [https://www.amd.com/en/product/12251 "AMD EPYC™ 9654P"]. AMD.com. Retrieved February 2023.
* {{cite techdoc|title=Revision Guide for AMD Family 19h Models 10h-1Fh Processors|url=https://www.amd.com/system/files/TechDocs/57095-PUB_1.00.pdf|publ=AMD|pid=57095|rev=1.00|date=2022-12-09}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 9654P - AMD#pcie +
base frequency	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
clock multiplier	24 +
core count	96 +
core family	25 +
core model	17 +
core name	Genoa +
core stepping	B1 +
cpuid	0x00A10F11 +
designer	AMD +
die count	13 +
family	EPYC +
first launched	November 10, 2022 +
full page name	amd/epyc/9654p +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	6,144 KiB (6,291,456 B, 6 MiB) +
l1d$ description	8-way set associative +
l1d$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l1i$ description	8-way set associative +
l1i$ size	3,072 KiB (3,145,728 B, 3 MiB) +
l2$ description	8-way set associative +
l2$ size	96 MiB (98,304 KiB, 100,663,296 B, 0.0938 GiB) +
l3$ description	16-way set associative +
l3$ size	384 MiB (393,216 KiB, 402,653,184 B, 0.375 GiB) +
ldate	November 10, 2022 +
manufacturer	TSMC +
market segment	Server +
max cpu count	1 +
max memory	6,291,456 MiB (6,442,450,944 KiB, 6,597,069,766,656 B, 6,144 GiB, 6 TiB) +
max memory bandwidth	429.153 GiB/s (439,453.125 MiB/s, 460.8 GB/s, 460,800 MB/s, 0.419 TiB/s, 0.461 TB/s) +
max memory channels	12 +
max sata ports	32 +
max usb ports	4 +
microarchitecture	Zen 4 +
model number	9654P +
name	EPYC 9654P +
package	SP5 +
part number	100-100000803 + and 100-100000803WOF +
process	5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) +
release price	$ 10,625.00 (€ 9,562.50, £ 8,606.25, ¥ 1,097,881.25) +
release price (tray)	$ 10,625.00 (€ 9,562.50, £ 8,606.25, ¥ 1,097,881.25) +
series	9004 +
smp max ways	1 +
socket	Socket SP5 +
supported memory type	DDR5-4800 +
tdp	360 W (360,000 mW, 0.483 hp, 0.36 kW) +
tdp down	320 W (320,000 mW, 0.429 hp, 0.32 kW) +
tdp up	400 W (400,000 mW, 0.536 hp, 0.4 kW) +
technology	CMOS +
thread count	192 +
turbo frequency	3,550 MHz (3.55 GHz, 3,550,000 kHz) +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +