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{{core | {{core | ||
|name=Rome | |name=Rome | ||
− | |image= | + | |no image=No |
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|developer=AMD | |developer=AMD | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
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|first launched=August 7, 2019 | |first launched=August 7, 2019 | ||
|isa=x86-64 | |isa=x86-64 | ||
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|microarch=Zen 2 | |microarch=Zen 2 | ||
|word=64 bit | |word=64 bit | ||
|proc=7 nm | |proc=7 nm | ||
+ | |proc 2=14 nm | ||
|tech=CMOS | |tech=CMOS | ||
|package name 1=amd,socket_sp3 | |package name 1=amd,socket_sp3 | ||
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|successor=Milan | |successor=Milan | ||
|successor link=amd/cores/milan | |successor link=amd/cores/milan | ||
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}} | }} | ||
− | '''Rome''' | + | '''Rome''' codename for [[AMD]]'s high-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen 2|l=arch}} microarchitecture serving as a successor to {{\\|Naples}}. Rome-based chips are fabricated on TSMC [[7 nm process]] with some components made on GlobalFoundries [[14 nm process]]. |
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− | Rome-based | ||
[[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | [[File:amd epyc rodmap.png|right|thumb|AMD datacenter roadmap]] | ||
== Overview == | == Overview == | ||
− | AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture | + | AMD Rome [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Rome SoCs support both single and 2-way multiprocessing with up to a maximum of 64 cores (and 128 threads) per processor for a total of up to 128 cores (and 256 threads) for a 2-way MP system. Those SoCs support 128 PCIe lanes each. Rome is backward platform/socket (Socket SP3) compatible with {{\\|Naples}} and forward-compatible with {{\\|Milan}}. |
=== Common Features === | === Common Features === | ||
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* Octa-channel Memory | * Octa-channel Memory | ||
** Up to DDR4-3200 ECC | ** Up to DDR4-3200 ECC | ||
− | ** Up to 4 [[TiB]] | + | ** Up to 4 [[TiB]] (8 TiB in 2MP) |
*** Up to 16 x 256 GiB @ 1.2 V | *** Up to 16 x 256 GiB @ 1.2 V | ||
*** RDIMM/LRDIMM/3DS/NVDIMM | *** RDIMM/LRDIMM/3DS/NVDIMM | ||
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<table class="comptable sortable tc5 tc6"> | <table class="comptable sortable tc5 tc6"> | ||
{{comp table header|main|10:List of Rome Processors}} | {{comp table header|main|10:List of Rome Processors}} | ||
− | {{comp table header|cols|Family | + | {{comp table header|cols|Family|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}} |
− | + | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome]] | |
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− | {{#ask: [[Category:microprocessor models by amd]] [[core name::Rome | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?microprocessor family | |?microprocessor family | ||
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|?first launched | |?first launched | ||
|?core count | |?core count | ||
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=11 |
|mainlabel=- | |mainlabel=- | ||
|valuesep=, | |valuesep=, |
Facts about "Rome - Cores - AMD"
back image | + |
designer | AMD + |
first announced | May 16, 2017 + |
first launched | August 7, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | + |
main image caption | Package front + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture | Zen 2 + |
name | Rome + |
package | FCLGA-4094 + and SP3 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-4094 + and SP3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |