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Latest revision | Your text | ||
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** Up to DDR4 2400 MT/s | ** Up to DDR4 2400 MT/s | ||
* 12 PCIe lanes (1x8 for GPU + 1x4 for storage) | * 12 PCIe lanes (1x8 for GPU + 1x4 for storage) | ||
− | * | + | * [[4 cores]] / 8 threads |
* 35 / 15 W TDP | * 35 / 15 W TDP | ||
** Configurable TDP-down of 12 W and a TDP-up of 25/35 W | ** Configurable TDP-down of 12 W and a TDP-up of 25/35 W |
Facts about "Picasso - Cores - AMD"
designer | AMD + |
first announced | January 6, 2019 + |
first launched | January 6, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen+ + |
name | Picasso + |
package | FP5 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |