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Latest revision | Your text | ||
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|clock min=2,100 MHz | |clock min=2,100 MHz | ||
|clock max=2,600 MHz | |clock max=2,600 MHz | ||
− | |||
|predecessor=Raven Ridge | |predecessor=Raven Ridge | ||
|predecessor link=amd/cores/raven ridge | |predecessor link=amd/cores/raven ridge | ||
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== Overview == | == Overview == | ||
− | Picasso is an SoC for the mobile segment | + | Picasso is an SoC for the mobile segment based on the {{amd|Zen+|l=arch}} microarchitecture incorporating a {{amd|Vega|l=arch}} GPU. |
=== Common Features === | === Common Features === | ||
− | All | + | All Raven Ridge processors have the following: |
* Up to 32/64 [[GiB]] of dual-channel memory | * Up to 32/64 [[GiB]] of dual-channel memory | ||
** Up to DDR4 2400 MT/s | ** Up to DDR4 2400 MT/s | ||
* 12 PCIe lanes (1x8 for GPU + 1x4 for storage) | * 12 PCIe lanes (1x8 for GPU + 1x4 for storage) | ||
− | * | + | * [[4 cores]] / 4 or 8 threads (not all models have [[SMT]]) |
− | * | + | * 15 W TDP with configurable TDP-down/up |
− | |||
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
* {{amd|Precision Boost 2}}, 2-way [[SMT]], {{amd|mXFR}} | * {{amd|Precision Boost 2}}, 2-way [[SMT]], {{amd|mXFR}} | ||
* Graphics | * Graphics | ||
− | ** {{amd|Radeon Vega | + | ** {{amd|Radeon Vega 10}}/{{amd|Radeon Vega 8|8}}/{{amd|Radeon Vega 6|6}}/{{amd|Radeon Vega 3|3}} ({{amd|Vega|l=arch}}) |
** Up to 1.4 GHz | ** Up to 1.4 GHz | ||
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<table class="comptable sortable tc4 tc5 tc6 tc7 tc8 tc10"> | <table class="comptable sortable tc4 tc5 tc6 tc7 tc8 tc10"> | ||
{{comp table header|main|9:Processor}} | {{comp table header|main|9:Processor}} | ||
− | {{comp table header|main|7: | + | {{comp table header|main|7:Processor|2:Integrated Graphics}} |
{{comp table header|cols|Family|Launched|Cores|Threads|Frequency|Turbo|TDP|GPU|Frequency}} | {{comp table header|cols|Family|Launched|Cores|Threads|Frequency|Turbo|TDP|GPU|Frequency}} | ||
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Picasso]] | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Picasso]] | ||
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|?thread count | |?thread count | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|?tdp | |?tdp | ||
|?integrated gpu | |?integrated gpu | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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== See also == | == See also == | ||
{{amd zen+ core see also}} | {{amd zen+ core see also}} |
Facts about "Picasso - Cores - AMD"
designer | AMD + |
first announced | January 6, 2019 + |
first launched | January 6, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen+ + |
name | Picasso + |
package | FP5 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |