From WikiChip
Editing amd/cores/picasso
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 15: | Line 15: | ||
|clock min=2,100 MHz | |clock min=2,100 MHz | ||
|clock max=2,600 MHz | |clock max=2,600 MHz | ||
− | |||
|predecessor=Raven Ridge | |predecessor=Raven Ridge | ||
|predecessor link=amd/cores/raven ridge | |predecessor link=amd/cores/raven ridge | ||
Line 22: | Line 21: | ||
}} | }} | ||
'''Picasso''' is codename for [[AMD]] series of mainstream mobile and desktop APUs based on the {{amd|Zen+|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures succeeding {{\\|Raven Ridge}}. Picasso processors are fabricated on GlobalFoundries [[12 nm process]] and incorporate [[four cores]]. | '''Picasso''' is codename for [[AMD]] series of mainstream mobile and desktop APUs based on the {{amd|Zen+|l=arch}} CPU and {{amd|Vega|l=arch}} GPU microarchitectures succeeding {{\\|Raven Ridge}}. Picasso processors are fabricated on GlobalFoundries [[12 nm process]] and incorporate [[four cores]]. | ||
+ | |||
+ | {{future information}} | ||
== Overview == | == Overview == | ||
− | + | {{empty section}} | |
=== Common Features === | === Common Features === | ||
All Picasso processors have the following: | All Picasso processors have the following: | ||
− | + | ||
− | + | {{empty section}} | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Picasso Processors == | == Picasso Processors == | ||
Line 51: | Line 43: | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable | + | <table class="comptable sortable tc5 tc6 tc11 tc12"> |
− | {{comp table header|main| | + | {{comp table header|main|11:List of Picasso Processors}} |
− | {{comp table header|main| | + | {{comp table header|main|9:Processor|2:Features}} |
− | {{comp table header|cols|Family|Launched|Cores|Threads|Frequency|Turbo|TDP| | + | {{comp table header|cols|Family|Price|Launched|Cores|Threads|Frequency|Turbo|TDP|Max Memory|XFR|PB Overdrive}} |
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Picasso]] | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[core name::Picasso]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
|?microprocessor family | |?microprocessor family | ||
+ | |?release price | ||
|?first launched | |?first launched | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
|?base frequency#GHz | |?base frequency#GHz | ||
− | |?turbo frequency#GHz | + | |?turbo frequency (1 core)#GHz |
|?tdp | |?tdp | ||
− | |? | + | |?max memory#GiB |
− | |? | + | |?has amd extended frequency range |
+ | |?has amd precision boost overdrive | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=13:12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
Line 75: | Line 69: | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== See also == | == See also == | ||
{{amd zen+ core see also}} | {{amd zen+ core see also}} |
Facts about "Picasso - Cores - AMD"
designer | AMD + |
first announced | January 6, 2019 + |
first launched | January 6, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen+ + |
name | Picasso + |
package | FP5 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |