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On a miss, a [[pseudo-random number generator]] is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM. | On a miss, a [[pseudo-random number generator]] is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM. | ||
− | The CAM consists of individual cells of [[six-transistor storage elements]] with a three-transistor [[comparators]]. The cell size was reported by Acorn to be 31.2 µm x 36.8 µm (1148.16 µm²) on a [[1.5 µm process]]. The entry matching and address encoding logic uses dynamic logic in order to reduce power. The [[RAM]] is arranged in array of 128 x 256 cells with a 3-bit column | + | The CAM consists of individual cells of [[six-transistor storage elements]] with a three-transistor [[comparators]]. The cell size was reported by Acorn to be 31.2 µm x 36.8 µm (1148.16 µm²) on a [[1.5 µm process]]. The entry matching and address encoding logic uses dynamic logic in order to reduce power. The [[RAM]] is arranged in array of 128 x 256 cells with a 3-bit column elect, producing a 32-bit output. The SRAM cells used were standard [[6T]] SRAM cells measuring 19.6 µm x 28.4 µm. Self-timing logic is used to disable the 32 [[sense amplifiers]] when the data becomes valid in order to reduce power. |
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Facts about "ARM3 - Microarchitectures - Acorn"
codename | ARM3 + |
core count | 1 + |
designer | Acorn Computers + |
first launched | 1989 + |
full page name | acorn/microarchitectures/arm3 + |
instance of | microarchitecture + |
instruction set architecture | ARMv2a + |
manufacturer | VLSI Technology + and Sanyo + |
microarchitecture type | CPU + |
name | ARM3 + |
pipeline stages | 3 + |
process | 1,500 nm (1.5 μm, 0.0015 mm) + |