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|l1 per=core
 
|l1 per=core
 
|l1 desc=64-way set associative
 
|l1 desc=64-way set associative
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|core name=ARM3
 
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|core name 2=ARM250
 
 
|predecessor=ARM2
 
|predecessor=ARM2
 
|predecessor link=acorn/microarchitectures/arm2
 
|predecessor link=acorn/microarchitectures/arm2
 
|successor=ARM6
 
|successor=ARM6
 
|successor link=arm holdings/microarchitectures/arm6
 
|successor link=arm holdings/microarchitectures/arm6
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|successor 2=ARM250
 
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|successor 2 link=arm holdings/microarchitectures/arm250
 
 
}}
 
}}
 
'''ARM3''' is the second-generation commercial [[ARM]] implementation designed by [[Acorn Computers]] as a successor to the {{\\|ARM2}}.
 
'''ARM3''' is the second-generation commercial [[ARM]] implementation designed by [[Acorn Computers]] as a successor to the {{\\|ARM2}}.
  
 
== History ==
 
== History ==
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{{see also|arm/history|l1=ARM's History}}
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The ARM3 builds on the success of the {{\\|ARM2}} with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 was designed by a team of four engineers in nine months. The ARM3 can operate at up to 25 MHz with a peak performance of 25 MIPS and a sustainable performance of 12 MIPS.
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The ARM3 builds on the success of the {{\\|ARM2}} with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 was designed by a team of four engineers in nine months and was introduced in [[1989]]. The ARM3 initially appeared with a 25 MHz crystal, In the Acorn A5000, with a peak performance of 25 MIPS and a sustainable performance of 12.72 MIPS. Later Acorn A540 and A5000 were supplied with ARM3 clocked the chip at 33MHz, with 3rd parties supplying chips clocked at 36 MHZ, to upgrade earlier ARM2 machines, from a sustained 4.85 to 17.44 MIPS.
 
  
 
== Process Technology ==
 
== Process Technology ==
 
{{see also|1.5 µm process}}
 
{{see also|1.5 µm process}}
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The ARM3 was implemented on a [[1.5 µm]] double-level metal (DLM) [[CMOS]] process.
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The ARM3 was implemented on a [[1.5 µm]] double-level metal [[CMOS]] process.
  
 
== Architecture ==
 
== Architecture ==
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* <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible)
 
* <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible)
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=== Block Diagram ===
 
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==== Entire Chip ====
 
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: [[File:arm3 block diagram.svg|600px]]
 
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==== Core ====
 
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: [[File:arm2 block diagram.svg|650px]]
 
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
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*** Write-through policy
 
*** Write-through policy
 
*** Per core
 
*** Per core
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* System DRAM
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** System DRAM
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** Up to 64 MiB
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*** Up to 64 MiB
  
 
== Overview ==
 
== Overview ==
 
=== Control ===
 
=== Control ===
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The ARM3's control logic is a state machine implemented as three [[PLA]]s. Layout was generated automatically using EDA tools using [[Psuedo nMOS]] logic in order to save on space, albeit at the slight expense of static power dissipation.
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The ARM3's control logic is a state machine implemented as three [[PLA]]s. Layout was generated automatically using [[Psuedo nMOS]] in order to save on space, albeit at the slight expense of static power dissipation.
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=== Core ===
 
=== Core ===
 
==== Pipeline ====
 
==== Pipeline ====
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{{main|acorn/microarchitectures/arm2#Pipeline|l1=ARM2 Pipeline}}
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{{main|arm holdings/microarchitectures/arm2#Pipeline|l1=ARM2 Pipeline}}
 
ARM3's pipeline is identical to the ARM2.
 
ARM3's pipeline is identical to the ARM2.
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=== Clock Generator ===
 
=== Clock Generator ===
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To increase performance, Acorn needed to increase the clock speed. This was not possible without leaving commodity DRAM for higher speed and more expensive DRAM. The alternative approach Acorn went with is an intermediate cache on-die. The ARM3 has two clock inputs, one fast one for the internal cache and one slower one for the external memory accesses. The two inputs are entirely independent allowing the system to optimize for both (fast cache and slower memory) at the same time.
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{{empty section}}
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=== Coprocessor Interface ===
 
=== Coprocessor Interface ===
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Acorn introduced cache with the ARM3. This meant that most instructions are now coming from the on-chip cache instead of system memory. The way the coprocessor was originally designed in the {{\\|ARM2}} meant that the coprocessor could simply access its instructions from memory. This was no longer compatible with the new design. Acorn solved this problem by making the coprocessor lag behind exactly one cycle. Instructions that are identified as being coprocessor instructions are broadcasted off-chip on the following cycle. This was done using the processor's 32-bit data port along with timing and handshaking signals.
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{{empty section}}
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=== Cache ===
 
=== Cache ===
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[[File:arm3 cache.svg|right|500px]]
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{{empty section}}
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The ARM3's cache consists of a RAM and 4 tag [[CAM]] banks of 64 22-bit entries each for 64-way set associative. The choice of a 4-way split was entirely driven by the great reduction in power dissipation (so only 1/4 of the CAM has to be active at any one time), at the cost of negligible performance. Each CAM entry refers to one line of data in the RAM. Each line consists of four 32-bit words (i.e., 128 bit lines) with the low-order address bits being used for the select lines.
 
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On a miss, a [[pseudo-random number generator]] is used to select an entry to evict and replace. On replacement a full line of four words is fetched from memory to minimize consecutive read operations. The cache uses a write-through update policy to ensure consistency. On a hit the appropriate line address are generated to be retrieved by the RAM.
 
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The CAM consists of individual cells of [[six-transistor storage elements]] with a three-transistor [[comparators]]. The cell size was reported by Acorn to be 31.2 µm x 36.8 µm (1148.16 µm²) on a [[1.5 µm process]]. The entry matching and address encoding logic uses dynamic logic in order to reduce power. The [[RAM]] is arranged in array of 128 x 256 cells with a 3-bit column select, producing a 32-bit output. The SRAM cells used were standard [[6T]] SRAM cells measuring 19.6 µm x 28.4 µm. Self-timing logic is used to disable the 32 [[sense amplifiers]] when the data becomes valid in order to reduce power.
 
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{{clear}}
 
  
 
== Die ==
 
== Die ==
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== All ARM3 Chips ==
 
== All ARM3 Chips ==
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{{comp table start}}
 
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<table class="comptable sortable tc11 tc12 tc13">
 
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of ARM3-based Processors</th></tr>
 
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{{comp table header 1|cols=Process, Launched, Frequency, Power Dissipation, Max Memory}}
 
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{{#ask: [[Category:all microprocessor models]] [[instance of::microprocessor]] [[microarchitecture::ARM3]]
 
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|?model number
 
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|?base frequency#MHz
 
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{{comp table count|ask=[[Category:all microprocessor models]] [[instance of::microprocessor]] [[microarchitecture::ARM3]]}}
 
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== References ==
 
== References ==
 
* Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.
 
* Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.

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Facts about "ARM3 - Microarchitectures - Acorn"
RDF feed
codenameARM3 +
core count1 +
designerAcorn Computers +
first launched1989 +
full page nameacorn/microarchitectures/arm3 +
instance ofmicroarchitecture +
instruction set architectureARMv2a +
manufacturerVLSI Technology + and Sanyo +
microarchitecture typeCPU +
nameARM3 +
pipeline stages3 +
process1,500 nm (1.5 μm, 0.0015 mm) +