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{{lithography processes}} | {{lithography processes}} | ||
− | The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin | + | The '''5 nanometer (5 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[7 nm lithography process|7 nm process]] node. Commercial [[integrated circuit]] manufacturing using 5 nm process is set to begin sometimes around 2020. |
The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | The term "5 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor. | ||
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=== Intel === | === Intel === | ||
− | ==== | + | ==== P1278 ==== |
− | Intel | + | Intel's 5-nanometer process node is expected to ramp around the 2023 timeframe. |
=== TSMC === | === TSMC === | ||
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The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, 5 nm makes extensive use of [[EUV]] for more critical layers in order to reduce the [[multi-patterning]] complexity. It is believed that TSMC N5 process uses 11-13 EUV masks in order to replace about 35 immersion layers that would otherwise be required to produce the same pattern without EUV. In other words for TSMC to go from its [[N7]] node to its [[N5]] node would entail going from roughly 87 [[masks]] to 115 masks. The introduction of EUV reduced this number back down to around 81 masks. | The N5 node continues to use [[bulk silicon]] [[FinFET transistors]]. Leveraging their experience from 7+, 5 nm makes extensive use of [[EUV]] for more critical layers in order to reduce the [[multi-patterning]] complexity. It is believed that TSMC N5 process uses 11-13 EUV masks in order to replace about 35 immersion layers that would otherwise be required to produce the same pattern without EUV. In other words for TSMC to go from its [[N7]] node to its [[N5]] node would entail going from roughly 87 [[masks]] to 115 masks. The introduction of EUV reduced this number back down to around 81 masks. | ||
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At a high level, TSMC N5 is a high-density high-performance [[FinFET]] process designed for mobile SoCs and HPC applications. Fabrication makes extensive use of EUV at Fab 18, the company’s new 12-inch GigaFab located at the Southern Taiwan Science Park. TSMC says that its 5-nanometer process is 1.84x denser than its [[N7|7-nanometer node]]. TSMC also optimized analog devices where roughly 1.2x scaling has been achieved. TSMC reported the density for a typical mobile SoC which consists of 60% logic, 30% SRAM, and 10% analog/IO, their 5 nm technology scaling was projected to reduce chip size by 35%-40%. | At a high level, TSMC N5 is a high-density high-performance [[FinFET]] process designed for mobile SoCs and HPC applications. Fabrication makes extensive use of EUV at Fab 18, the company’s new 12-inch GigaFab located at the Southern Taiwan Science Park. TSMC says that its 5-nanometer process is 1.84x denser than its [[N7|7-nanometer node]]. TSMC also optimized analog devices where roughly 1.2x scaling has been achieved. TSMC reported the density for a typical mobile SoC which consists of 60% logic, 30% SRAM, and 10% analog/IO, their 5 nm technology scaling was projected to reduce chip size by 35%-40%. | ||
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! colspan="3" | N5 [[PPA]] vs. [[N7]] | ! colspan="3" | N5 [[PPA]] vs. [[N7]] | ||
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− | ! Speed @ | + | ! Speed @ iso-power !! Power @ iso-speed !! Max speed improvement<br>@ Vdd (eLVT) |
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| ~15% || ~30% || ~25% | | ~15% || ~30% || ~25% | ||
|} | |} | ||
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− | [[ | + | In order to improve the drive current, TSMC introduced a [[high-mobility channel]] (HMC) for its 5-nanometer [[FinFET devices]]. We believe TSMC is employing a SiGe channel for the pMOS devices. It has been suggested that the channel has 37% Ge composition. TSMC says that the HMC delivers 18% performance gain versus equivalent Si finFETs. A TEM of the full-strained HMC lattice is shown on the right. Despite aggressively tighter pitches, TSMC says metal lines RC and via resistance have been kept relatively similar to N7. TSMC says this was achieved by "using EUV patterning, innovative scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow." The improvements meant the interconnect RC did not worsen relative to N7 as N7 did relative to N16. |
− | Despite aggressively tighter pitches, TSMC says metal lines RC and via resistance have been kept relatively similar to N7. TSMC says this was achieved by "using EUV patterning, innovative scaled barrier/liner, ESL/ELK dielectrics, and Cu reflow." The improvements meant the interconnect RC did not worsen relative to N7 as N7 did relative to N16. | ||
− | The 5 nm node is expected to deliver a 15% improvement in performance at | + | The 5 nm node is expected to deliver a 15% improvement in performance at constant power or a 20% reduction in power at constant performance. In addition to the ultra-LVT (uLVT) that was offered with [[N7]], there is a new extreme-LVT (eLVT) which can push that 15% up to 25% higher speed at Vdd. Additionally, compared to the standard N5 cells, the HP cell variants can push that performance by another 10% at the cost of density. |
The N5 node makes use of a number of [[density boosters]] under a marketing term called "smart hyper-scaling features" (similar to Intel). N5 introduces [[single diffusion breaks]] in order to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented with at the N7 node, [[via pillars]] are also used extensively in the N5 node. TSMC makes extensive use of [[via pillars]] in N5 due to the three-fold increase of Mx resistance. | The N5 node makes use of a number of [[density boosters]] under a marketing term called "smart hyper-scaling features" (similar to Intel). N5 introduces [[single diffusion breaks]] in order to reduce cell spacing. Additionally, TSMC added the ability to drop the gate contact over the active region (COAG). Although originally experimented with at the N7 node, [[via pillars]] are also used extensively in the N5 node. TSMC makes extensive use of [[via pillars]] in N5 due to the three-fold increase of Mx resistance. | ||
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==== N5P ==== | ==== N5P ==== | ||
− | As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called '''N5 Performance-enhanced version''' ('''N5P'''). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at | + | As with their 7-nanometer process, TSMC will offer an optimized version of their N5 process called '''N5 Performance-enhanced version''' ('''N5P'''). This process uses the same design rules and is fully IP-compatible with N5. Through FEOL and MOL optimizations, N5P will offer 7% higher performance over N5 at iso-power or 15% lower power at iso-performance. Risk production for N5 is expected to start around the second half of 2020 with volume production starting sometimes in 2021. |
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=== Samsung === | === Samsung === | ||
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| Metal 1 || 28 nm || 0.70x | | Metal 1 || 28 nm || 0.70x | ||
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− | | Metal 2 || 36 nm || | + | | Metal 2 || 36 nm || 0.75x |
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− | | Metal 3 || 32 nm || 0. | + | | Metal 3 || 32 nm || 0.88x |
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| Metal 4 || 44 nm || 1.0x | | Metal 4 || 44 nm || 1.0x | ||
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* PEZY | * PEZY | ||
** {{pezy|PEZY-SC4}} | ** {{pezy|PEZY-SC4}} | ||
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{{expand list}} | {{expand list}} | ||
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* Samsung, Arm TechCon, 2019 | * Samsung, Arm TechCon, 2019 | ||
* TSMC, Arm TechCon, 2019 | * TSMC, Arm TechCon, 2019 | ||
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[[category:lithography]] | [[category:lithography]] |