Editing amd/packages/ft1 (section)

== Pin Map ==
:[[File:BGA-413 pinmap.svg|800px]]

FT1 pinout.
<!--
ALERT_L,T2,M_DATA[32],N23,SVC,J1,VDD_18_DAC,W9
CLKIN_H,V2,M_DATA[33],P21,SVD,J2,VDD_33,A4
CLKIN_L,V1,M_DATA[34],T20,TCK,P1,VSS,A7
DAC_BLUE,A13,M_DATA[35],T23,TDI,N2,VSS,B7
DAC_BLUEB,B13,M_DATA[36],M20,TDO,N1,VSS,B11
DAC_GREEN,A12,M_DATA[37],P20,TDP1_AUXN,C2,VSS,B15
DAC_GREENB,B12,M_DATA[38],R23,TDP1_AUXP,B2,VSS,B17
DAC_HSYNC,E1,M_DATA[39],T22,TDP1_HPD,C1,VSS,B22
DAC_RED,C12,M_DATA[40],V20,TDP1_TXN[0],B8,VSS,C4
DAC_REDB,D13,M_DATA[41],V21,TDP1_TXN[1],A9,VSS,D5
DAC_SCL,F2,M_DATA[42],Y23,TDP1_TXN[2],C10,VSS,D7
DAC_SDA,D4,M_DATA[43],Y22,TDP1_TXN[3],B10,VSS,D9
DAC_VSYNC,E2,M_DATA[44],T21,TDP1_TXP[0],A8,VSS,D11
DAC_ZVSS,D12,M_DATA[45],U23,TDP1_TXP[1],B9,VSS,D14
DBRDY,M3,M_DATA[46],W23,TDP1_TXP[2],D10,VSS,D17
DBREQ_L,M1,M_DATA[47],Y21,TDP1_TXP[3],A10,VSS,D19
DISP_CLKIN_H,D2,M_DATA[48],Y20,TEST4,R1,VSS,E7
DISP_CLKIN_L,D1,M_DATA[49],AB22,TEST5,R2,VSS,E9
DMAACTIVE_L,T1,M_DATA[50],AC19,TEST6,R6,VSS,E12
DP_BLON,G2,M_DATA[51],AA18,TEST14,T5,VSS,E20
DP_DIGON,H2,M_DATA[52],AA23,TEST15,E4,VSS,F8
DP_VARY_BL,H1,M_DATA[53],AA20,TEST16,K4,VSS,F11
DP_ZVSS,H3,M_DATA[54],AB19,TEST17,L1,VSS,F13
LTDP0_AUXN,B3,M_DATA[55],Y18,TEST18,L2,VSS,G4
LTDP0_AUXP,A3,M_DATA[56],AC17,TEST19,M2,VSS,G5
LTDP0_HPD,D3,M_DATA[57],Y16,TEST25_H,K1,VSS,G7
LTDP0_TXN[0],A5,M_DATA[58],AB14,TEST25_L,K2,VSS,G9
LTDP0_TXN[1],C6,M_DATA[59],AC14,TEST28_H,L5,VSS,G12
LTDP0_TXN[2],B6,M_DATA[60],AC18,TEST28_L,M5,VSS,G20
LTDP0_TXN[3],C8,M_DATA[61],AB18,TEST31,M21,VSS,G22
LTDP0_TXP[0],B5,M_DATA[62],AB15,TEST33_H,J18,VSS,H6
LTDP0_TXP[1],D6,M_DATA[63],AC15,TEST33_L,J19,VSS,H11
LTDP0_TXP[2],A6,M_DM[0],D15,TEST34_H,U15,VSS,H13
LTDP0_TXP[3],D8,M_DM[1],B19,TEST34_L,T15,VSS,J4
M0_CS_L[0],T17,M_DM[2],D21,TEST35,H4,VSS,J5
M0_CS_L[1],W16,M_DM[3],H22,TEST36,N5,VSS,J7
M0_ODT[0],W19,M_DM[4],P23,TEST37,R5,VSS,J20
M0_ODT[1],V15,M_DM[5],V23,TEST38,K3,VSS,K10
M1_CS_L[0],U17,M_DM[6],AB20,THERMTRIP_L,U2,VSS,K14
M1_CS_L[1],V16,M_DM[7],AA16,TMS,P2,VSS,L4
M1_ODT[0],U19,M_DQS_H[0],A16,TRST_L,M4,VSS,L6
M1_ODT[1],W15,M_DQS_H[1],B20,VDDCR_CPU,E5,VSS,L8
M_ADD[0],R17,M_DQS_H[2],E23,VDDCR_CPU,E6,VSS,L11
M_ADD[1],H19,M_DQS_H[3],J22,VDDCR_CPU,F5,VSS,L13
M_ADD[2],J17,M_DQS_H[4],R22,VDDCR_CPU,F7,VSS,L20
M_ADD[3],H18,M_DQS_H[5],W22,VDDCR_CPU,G6,VSS,L22
M_ADD[4],H17,M_DQS_H[6],AC20,VDDCR_CPU,G8,VSS,M7
M_ADD[5],G17,M_DQS_H[7],AB16,VDDCR_CPU,H5,VSS,N4
M_ADD[6],H15,M_DQS_L[0],B16,VDDCR_CPU,H7,VSS,N6
M_ADD[7],G18,M_DQS_L[1],A20,VDDCR_CPU,J6,VSS,N8
M_ADD[8],F19,M_DQS_L[2],E22,VDDCR_CPU,J8,VSS,N11
M_ADD[9],E19,M_DQS_L[3],J23,VDDCR_CPU,L7,VSS,N13
M_ADD[10],T19,M_DQS_L[4],P22,VDDCR_CPU,M6,VSS,N20
M_ADD[11],F17,M_DQS_L[5],V22,VDDCR_CPU,M8,VSS,N22
M_ADD[12],E18,M_DQS_L[6],AC21,VDDCR_CPU,N7,VSS,P10
M_ADD[13],W17,M_DQS_L[7],AC16,VDDCR_CPU,R8,VSS,P14
M_ADD[14],E16,M_EVENT_L,N17,VDDCR_CPU_SENSE,G1,VSS,R4
M_ADD[15],G15,M_RAS_L,U18,VDDCR_NB,E8,VSS,R7
M_BANK[0],R18,M_RESET_L,L23,VDDCR_NB,E11,VSS,R20
M_BANK[1],T18,M_VREF,M23,VDDCR_NB,E13,VSS,T6
M_BANK[2],F16,M_WE_L,V17,VDDCR_NB,F9,VSS,T9
M_CAS_L,V19,M_ZVDDIO_MEM_S,M22,VDDCR_NB,F12,VSS,T11
M_CKE[0],F15,PROCHOT_L,U1,VDDCR_NB,G11,VSS,T13
M_CKE[1],E15,PWROK,T4,VDDCR_NB,G13,VSS,U4
M_CLK_H[0],M17,P_GPP_RXN[0],Y6,VDDCR_NB,H9,VSS,U5
M_CLK_H[1],M19,P_GPP_RXN[1],AC4,VDDCR_NB,H12,VSS,U7
M_CLK_H[2],N18,P_GPP_RXN[2],AA2,VDDCR_NB,K11,VSS,U12
M_CLK_H[3],L18,P_GPP_RXN[3],Y3,VDDCR_NB,K13,VSS,U20
M_CLK_L[0],M16,P_GPP_RXP[0],AA6,VDDCR_NB,L10,VSS,U22
M_CLK_L[1],M18,P_GPP_RXP[1],AB4,VDDCR_NB,L12,VSS,V8
M_CLK_L[2],N19,P_GPP_RXP[2],AA1,VDDCR_NB,L14,VSS,V9
M_CLK_L[3],L17,P_GPP_RXP[3],Y4,VDDCR_NB,M11,VSS,V11
M_DATA[0],B14,P_GPP_TXN[0],AC6,VDDCR_NB,M12,VSS,V13
M_DATA[1],A15,P_GPP_TXN[1],AC3,VDDCR_NB,M13,VSS,W1
M_DATA[2],A17,P_GPP_TXN[2],Y2,VDDCR_NB,N10,VSS,W2
M_DATA[3],D18,P_GPP_TXN[3],V4,VDDCR_NB,N12,VSS,W4
M_DATA[4],A14,P_GPP_TXP[0],AB6,VDDCR_NB,N14,VSS,W5
M_DATA[5],C14,P_GPP_TXP[1],AB3,VDDCR_NB,P11,VSS,W7
M_DATA[6],C16,P_GPP_TXP[2],Y1,VDDCR_NB,P13,VSS,W12
M_DATA[7],D16,P_GPP_TXP[3],V3,VDDCR_NB_SENSE,F4,VSS,W20
M_DATA[8],C18,P_UMI_RXN[0],Y12,VDDIO_MEM_S,E17,VSS,Y5
M_DATA[9],A19,P_UMI_RXN[1],Y10,VDDIO_MEM_S,G16,VSS,Y7
M_DATA[10],B21,P_UMI_RXN[2],AC10,VDDIO_MEM_S,G19,VSS,Y9
M_DATA[11],D20,P_UMI_RXN[3],AB7,VDDIO_MEM_S,J16,VSS,Y11
M_DATA[12],A18,P_UMI_RXP[0],AA12,VDDIO_MEM_S,L16,VSS,Y13
M_DATA[13],B18,P_UMI_RXP[1],AA10,VDDIO_MEM_S,L19,VSS,Y15
M_DATA[14],A21,P_UMI_RXP[2],AB10,VDDIO_MEM_S,N16,VSS,Y17
M_DATA[15],C20,P_UMI_RXP[3],AC7,VDDIO_MEM_S,R16,VSS,Y19
M_DATA[16],C23,P_UMI_TXN[0],AC12,VDDIO_MEM_S,R19,VSS,AA4
M_DATA[17],D23,P_UMI_TXN[1],AB11,VDDIO_MEM_S,U16,VSS,AA22
M_DATA[18],F23,P_UMI_TXN[2],Y8,VDDIO_MEM_S,W18,VSS,AB2
M_DATA[19],F22,P_UMI_TXN[3],AC8,VDDIO_MEM_S_SENSE,F3,VSS,AB5
M_DATA[20],C22,P_UMI_TXP[0],AB12,VDDPL_10,U11,VSS,AB9
M_DATA[21],D22,P_UMI_TXP[1],AC11,VDD_10,T12,VSS,AB13
M_DATA[22],F20,P_UMI_TXP[2],AA8,VDD_10,U13,VSS,AB17
M_DATA[23],F21,P_UMI_TXP[3],AB8,VDD_10,V12,VSS,AB21
M_DATA[24],H21,P_ZVDD_10,Y14,VDD_10,W13,VSS,AC5
M_DATA[25],H23,P_ZVSS,AA14,VDD_18,T7,VSS,AC9
M_DATA[26],K22,RESET_L,T3,VDD_18,U6,VSS,AC13
M_DATA[27],K21,RSVD,B4,VDD_18,U8,VSSBG_DAC,A11
M_DATA[28],G23,RSVD,V5,VDD_18,U9,VSS_SENSE,F1
M_DATA[29],H20,RSVD,W11,VDD_18,V7
M_DATA[30],K20,SIC,P3,VDD_18,W6
M_DATA[31],K23,SID,P4,VDD_18,W8
-->

=== Pin Description ===
{| class="wikitable sortable"
!Signal!!Type!!Description
|-
|M_ADD[15:0]||O-IO-S||DRAM Column/Row Address
|-
|M_BANK[2:0]||O-IO-S||DRAM Bank Address
|-
|M_CAS_L||O-IO-S||DRAM Column Address Strobe
|-
|M_CKE[1:0]||O-IO-S||DRAM Clock Enable
|-
|M_CLK_H/L[3:0]||O-IO-S||DRAM Differential Clock
|-
|M_DATA[63:0]||B-IO-S||DRAM Data Bus
|-
|M_DM[7:0]||O-IO-S||DRAM Data Mask
|-
|M_DQS_H/L[7:0]||B-IO-D||DRAM Differential Data Strobe
|-
|M_EVENT_L||I-IO-S||DRAM Thermal Event
|-
|M_RAS_L||O-IO-S||DRAM Row Address Strobe
|-
|M_RESET_L||O-IO-S||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
|-
|M_VREF||VREF||Memory Interface Voltage Reference
|-
|M_WE_L||O-IO-S||DRAM Write Enable
|-
|M0_CS_L[1:0], M1_CS_L[1:0]||O-IO-S||DRAM Chip Selects
|-
|M0_ODT[1:0], M1_ODT[1:0]||O-IO-S||DRAM Enable Pin for On Die Termination
|-
|M_ZVDDIO_MEM_S||A||DRAM Interface Drive-Strength Compensation Resistor to VDDIO
|-
|P_GPP_RXP/RXN[3:0]||I-PCIe-D||General Purpose External PCIe Receive Data Differential Pairs
|-
|P_GPP_TXP/TXN[3:0]||O-PCIe-D||General Purpose External PCIe Transmit Data Differential Pairs
|-
|P_UMI_RXP/RXN[3:0]||I-PCIe-D||Unified Media Interface Receive Data Differential Pairs
|-
|P_UMI_TXP/TXN[3:0]||O-PCIe-D||Unified Media Interface Transmit Data Differential Pairs
|-
|P_ZVDD_10||A||PCIe Drive-Strength Compensation Resistor to P_VDD_10 Power Supply
|-
|P_ZVSS||A||PCIe Drive-Strength Compensation Resistor to VSS
|-
|LTDP0_TXP/TXN[3:0]||O-PCIe-D||{{abbr|LVDS}}/{{abbr|TMDS}} DisplayPort 0 Differential Transmitter
|-
|TDP1_TXP/TXN[3:0]||O-PCIe-D||TMDS DisplayPort 1 Differential Transmitter
|-
|LTDP0/TDP1_AUXP/AUXN||B-IO33-D||DisplayPort Auxiliary Channel
|-
|LTDP0/TDP1_HPD||I-IO33-S||DisplayPort Hot Plug Detect
|-
|DP_BLON||O-IO33-S||Display Panel Backlight Enable
|-
|DP_DIGON||O-IO33-S||Display Panel Power Enable
|-
|DP_VARY_BL||O-IO33-S||Display Backlight Brightness Control
|-
|DP_ZVSS||A||DP Drive-Strength Compensation Resistor to VSS
|-
|DAC_RED, DAC_REDB||A||Red for Video Monitor Output
|-
|DAC_GREEN, DAC_GREENB||A||Green for Video Monitor Output
|-
|DAC_BLUE, DAC_BLUEB||A||Blue for Video Monitor Output
|-
|DAC_HSYNC, DAC_VSYNC||O-IO33-S||Display Horizontal, Vertical Sync
|-
|DAC_SCL||O-IO33-OD||{{abbr|I<sup>2</sup>C}} Clock for Display (to video monitor)
|-
|DAC_SDA||B-IO33-OD||I<sup>2</sup>C Data for Display
|-
|DAC_ZVSS||A||DAC Drive-Strength Compensation Resistor to DAC Ground Pin
|-
|CLKIN_H/L||I-IO18-D||100&nbsp;MHz PLL Differential Reference Clock
|-
|DISP_CLKIN_H/L||I-IO18-D||100&nbsp;MHz Display Controller Reference Clock
|-
|DMAACTIVE_L||I-IO18-S||Indicated System DMA Activity
|-
|PWROK||I-IO18-S||Voltages and CLKIN have reached specified operation
|-
|RESET_L||I-IO18-S||Processor Reset
|-
|ALERT_L||O-IO33-OD||Programmable pin that can indicate different events, including a {{abbr|SB-TSI}} interrupt
|-
|PROCHOT_L||B-IO33-OD||Processor in {{x86|Hardware Thermal Control|HTC}}-active state
|-
|SIC||I-IO33-S||Sideband Interface ({{abbr|SB-TSI}}) Clock
|-
|SID||B-IO33-OD||Sideband Interface Data
|-
|THERMTRIP_L||O-IO33-OD||{{x86|Thermal protection|Thermal Sensor Trip}} Output
|-
|DBREQ_L||I-IO18-S||Debug Request
|-
|DBRDY||O-IO18-S||Debug Ready
|-
|TCK||I-IO18-S||{{abbr|JTAG}} Clock
|-
|TDI||I-IO18-S||JTAG Data Input
|-
|TDO||O-IO18-S||JTAG Data Output
|-
|TMS||I-IO18-S||JTAG Mode Select
|-
|TRST_L||I-IO18-S||JTAG Reset
|-
|TEST*||||Test signal
|-
|SVC||O-IO18-S||Serial VID Interface Clock
|-
|SVD||B-IO18-OD||Serial VID Interface Data
|-
|VDDCR_CPU||S||Core Power Supply
|-
|VDDCR_CPU_SENSE||A||VDDCR_CPU Voltage Monitor Pin
|-
|VDDCR_NB||S||Northbridge Power Supply
|-
|VDDCR_NB_SENSE||A||VDDCR_NB Voltage Monitor Pin
|-
|VDDIO_MEM_S||S||DRAM I/O Ring Power Supply
|-
|VDDIO_MEM_S_SENSE||A||VDDIO_MEM_S Voltage Monitor Pin
|-
|VDD_10||S||1.05&nbsp;V Supply Pins
|-
|VDDPL_10||S||1.05&nbsp;V Supply Pin for System PLL
|-
|VDD_18||S||1.8&nbsp;V Supply Pins
|-
|VDD_18_DAC||S||1.8&nbsp;V Supply Pin for DAC
|-
|VDD_33||S||3.3&nbsp;V Supply Pin
|-
|VSS||S||Ground
|-
|VSS_SENSE||A||VSS Voltage Monitor Pin
|-
|VSSBG_DAC||S||DAC Ground
|-
|RSVD||||Reserved
|}

==== Pin Types ====
{| class="wikitable"
|I/O-PCIe-D||Input / Output, PCIe Voltage Domain, Differential
|-
|I/O/B-IO-D/S/OD||Input / Output / Bidirectional, VDDIO_MEM_S, Differential / Single-Ended / Open Drain
|-
|I/O/B-IO18-D/S/OD||Input / Output / Bidirectional, VDD_18, Differential / Single-Ended / Open Drain
|-
|I/O/B-IO33-D/S/OD||Input / Output / Bidirectional, VDD_33, Differential / Single-Ended / Open Drain
|-
|A||Analog
|-
|S||Supply Voltage
|}
designer	AMD +
first launched	January 4, 2011 +
instance of	package +
market segment	Mobile + and Embedded +
microarchitecture	Bobcat +
name	FT1 +
package	FT1 + and UOB413 +
package contacts	413 +
package height	1.92 mm (0.0756 in) +
package length	19 mm (1.9 cm, 0.748 in) +
package pitch	0.8 mm (0.0315 in) +
package type	FC-OBGA +
package width	19 mm (1.9 cm, 0.748 in) +
tdp	18 W (18,000 mW, 0.0241 hp, 0.018 kW) +