Editing marvell/armada/610 (section)

===NAND Flash Controller===
* ONFI compliant controller supporting SLC and MLC NAND, x8 & x16, small block and large block
* 2 Chip Selects with up to 64GB of address space
* Support for 2 KB and 4 KB page sizes
* 2-bit detect/1-bit correct ECC & 16-bit correct BCH
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
core count	1 +
core name	Sheeva PJ4 +
designer	Marvell +
family	ARMADA 600 +
first announced	October 19, 2009 +
first launched	January 5, 2010 +
full page name	marvell/armada/610 +
has ecc memory support	false +
instance of	microprocessor +
integrated gpu	GC860 +
integrated gpu designer	Vivante +
io voltage	1.5 V (15 dV, 150 cV, 1,500 mV) +, 3 V (30 dV, 300 cV, 3,000 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
io voltage tolerance	0.3 V +
isa	ARMv5 + and ARMv6 +
isa family	ARM +
l1$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1d$ size	32 KiB (32,768 B, 0.0313 MiB) +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
l2$ size	0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldate	January 5, 2010 +
manufacturer	TSMC +
market segment	Mobile +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	7.942 GiB/s (8,132.608 MiB/s, 8.528 GB/s, 8,527.658 MB/s, 0.00776 TiB/s, 0.00853 TB/s) +
max memory channels	1 +
microarchitecture	Sheeva PJ4 +
model number	610 +
name	ARMADA 610 +
part number	88AP610 +
platform	ARMADA +
process	55 nm (0.055 μm, 5.5e-5 mm) +
series	600 +
smp max ways	1 +
supported memory type	DDR2-800 + and DDR3-1066 +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +