Editing intel/microarchitectures/palm cove (section)

=== Key changes from {{\\|Skylake (Client)}}===
* [[10 nm process]] (From [[14 nm]])
* Front End
** LSD is re-enabled (See {{\\|skylake_(server)#Front-end|Skylake § Front-end}} for details)
** 50% smaller L1 instruction cache 4K page TLB (64-entry, down from 128)
* Back-end
** Execution units
*** Port 4 now performs 512b stores (from 256b)
*** New 512b FMA unit on Port 0
*** New iDIV unit
* Memory subsystem
** Store is now 64B/cycle (from 32B/cycle)
** Load is now 2x64B/cycle (from 2x32B/cycle)

{{expand list}}

==== New instructions ====
Cannon Lake introduced a number of {{x86|extensions|new instructions}}:

* {{x86|AVX-512|<code>AVX-512</code>}}, specifically:
** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation
** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection
** {{x86|AVX512BW|<code>AVX512BW</code>}} - AVX-512 Byte and Word
** {{x86|AVX512DQ|<code>AVX512DQ</code>}} - AVX-512 Doubleword and Quadword 
** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length
** {{x86|AVX512IFMA|<code>AVX512IFMA</code>}} - AVX-512 Integer Fused Multiply-Add
** {{x86|AVX512VBMI|<code>AVX512VBMI</code>}} - AVX-512 Vector Bit Manipulation
* {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
* {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension
codename	Palm Cove +
core count	2 +
designer	Intel +
first launched	2018 +
full page name	intel/microarchitectures/palm cove +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Palm Cove +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	10 nm (0.01 μm, 1.0e-5 mm) +