Editing cavium/thunderx2/cn9960 (section)

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=2 TiB
|controllers=2
|channels=4
|max bandwidth=79.47 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	ThunderX2 CN9960 - Cavium#pcie +
base frequency	1,600 MHz (1.6 GHz, 1,600,000 kHz) +, 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) +
core count	16 +
designer	Cavium +
family	ThunderX2 +
first announced	May 7, 2018 +
first launched	May 7, 2018 +
full page name	cavium/thunderx2/cn9960 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8.1 +
isa family	ARM +
l1$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size	16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldate	May 7, 2018 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
max sata ports	2 +
max usb ports	2 +
microarchitecture	Vulcan +
model number	CN9960 +
name	ThunderX2 CN9960 +
package	FCLGA-4077 +
part number	CN9960-2200LG4077-Y21-G +, CN9960-2000LG4077-Y21-G +, CN9960-1800LG4077-Y21-G + and CN9960-1600LG4077-Y21-G +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2666 +
technology	CMOS +
thread count	64 +
word size	64 bit (8 octets, 16 nibbles) +