Editing cavium/octeon/cn3010-500bg525-cp (section)

== Memory controller ==
{{memory controller
|type=DDR2-533
|ecc=Yes
|max mem=2 GiB
|controllers=1
|channels=1
|width=32 bit
|max bandwidth=1.986 GiB/s
|bandwidth schan=1.986 GiB/s
}}
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	1 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3010-500bg525-cp +
has ecc memory support	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description	64-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	2-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	4-way set associative +
l2$ size	0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3010-500 CP +
name	Cavium CN3010-500 CP +
part number	CN3010-500BG525-CP +
power dissipation	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3000 +
smp max ways	1 +
supported memory type	DDR2-533 +
technology	CMOS +
thread count	1 +
word size	64 bit (8 octets, 16 nibbles) +