Editing uc davis/kilocore (section)

== Architecture ==
The chip is designed as a [[massively parallel processor array]], with 992 cores arranged as a grid 32 by 31. Eight additional cores are found along with 12 memory modules of 64 KB SRAM each (for a total of 768 KB). Communication between cores is done via a dual-layer source-synchronous [[circuit-switched network]] and a very-small-area packet router (see [[wormhole routing]]). The circuit-switched network supports communication  between  adjacent and distant processors, as resources allow, with each link supporting a maximum rate of 28.5 Gbps. Maximum throughput is 45.5 Gbps per router. Both network types contribute to an array bisection bandwidth of '''4.2 Tbps'''.

=== Cores ===
Each core is an independent processing unit capable of issuing one instruction [[in-order]] per cycle. Instructions may come from the local instruction memory or they may be fetched from one of the independent memory module. Likewise data may come from the data memory or from the independent memory module.

Each core contains 128x40-bit local instruction memory. Data memory is also stored in each as 2 banks of 128x16-bit each (for a total of 256x16-bit). The core also has three data address generators, two 32x16 input FIFO buffers, a 16-bit fixed-point data path.

=== Memory Module ===
Each memory module contains 64 KB of SRAM and has an area of 0.164 mm². The module also contains two 32x16-bit FIFO buffers.

=== Floorplan ===
[[File:ucd kilocore floorplan.png|600px]]

Each core has an area of 0.055 mm² (232 µm x 239 µm) and contains 575,000 transistors. The SRAM memory module has an area of 0.164 mm² (367 µm x 446 µm).
base frequency	1,780 MHz (1.78 GHz, 1,780,000 kHz) +
core count	1,000 +
designer	UC Davis +, Brent Bohnenstiehl +, Aaron Stillmaker + and Bevan Baas +
die area	64 mm² (0.0992 in², 0.64 cm², 64,000,000 µm²) +
first announced	June 17, 2016 +
full page name	uc davis/kilocore +
instance of	microprocessor +
ldate	June 17, 2016 +
main image	+
main image caption	KiloCore on a daughterboard +
manufacturer	IBM +
name	KiloCore +
process	32 nm (0.032 μm, 3.2e-5 mm) +
technology	CMOS +
transistor count	621,000,000 +
word size	16 bit (2 octets, 4 nibbles) +