Editing amd/packages/socket fs1r2 (section)

=== Features ===
* 722-pin lidless micro pin grid array package, 1.2192 mm (0.048") pitch, 28 × 28 pins, 35 × 35 mm, organic substrate

* 2 × 64 bit DDR3 SDRAM interface up to 933 MHz, PC3-14900 (DDR3-1866), 29.9 GB/s
** Up to 2 SR UDIMMs or SODIMMs (1 per channel), no ECC support
** JEDEC 1.5V, 1.35V, 1.25V
** AMD Memory Controller PowerCap

* PCIe Gen 1.0 and 2.0 (5 GT/s)
** Configurable x8 or x16 external graphics card (GFX) link
** Configurable x4 General Purpose Ports
** x4 Unified Media Interface to FCH

* Four independent display controllers
** Six Digital Display Interfaces
*** 3 × single link
*** 3 × multiplexed, presumably each with 1x4 (dual link DVI 1x8) GFX lanes or 1x4 UMI lanes
** DisplayPort 1.2 up to 4096 × 2160 at 30 Hz and 30 bpp, eDP, DP++, DP audio, HDCP
** Single/dual link DVI 1.4a up to 2560 × 1600 at 60 Hz and 24 bpp, HDCP
** HDMI 1.4a up to 1920 × 1200 at 60 Hz and 24 bpp, 3D Video, HDCP
** VGA via FCH DP DAC

* Power Management
** AMD AllDay power technology
** ACPI P-states, processor power states C0, C1, C1E, C6, CC6, sleep states S0, S3, S4, S5
** PCIe core power gating
** PCIe speed power policy
** AMD Turbo CORE technology 3.0 with per core power gating

* Thermal Controls
** Sideband temperature control (SB-TSI)
** Hardware thermal control (HTC)
** Local hardware thermal control (LHTC)
** DRAM thermal protection
designer	AMD +
first launched	May 15, 2012 +
instance of	package +
market segment	Mobile +
microarchitecture	Piledriver +
name	Socket FS1r2 +
package	OPGA-722 +
package contacts	722 +
package length	35 mm (3.5 cm, 1.378 in) +
package pitch	1.219 mm (0.048 in) +
package type	Organic Micro Pin Grid Array +
package width	35 mm (3.5 cm, 1.378 in) +
socket	Socket FS1r2 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +