Editing amd/packages/socket swrx8

{{amd title|Socket sWRX8}}
{{package
|name=Socket sWRX8
|designer=AMD
|market=Workstation
|first launched=July 14, 2020
|microarch=Zen 2
|microarch 2=Zen 3
|tdp=280 W
|package name=sWRX8
|package name 2=FCLGA-4094
|package type=FC-OLGA
|package contacts=4094
|package dimension=75.40 mm
|package dimension 2=58.50 mm
|package dimension 3=6.26 mm
|pitch=0.87 mm
|pitch 2=1.00 mm
|socket type=SM-LGA
|socket name=sWRX8
|predecessor=Socket TR4
|predecessor link=amd/packages/socket tr4
|contemporary=Socket sTRX4
|contemporary link=amd/packages/socket strx4
|contemporary 2=Socket SP3
|contemporary 2 link=amd/packages/socket sp3
}}
'''Socket sWRX8''' is a microprocessor socket designed by [[AMD]] for workstation versions of their third and fourth generation {{amd|Ryzen Threadripper}} processors, the successor to {{\\|Socket TR4}}. Contemporary mainstream desktop, {{abbr|HEDT}}, and server processors use {{\\|Socket AM4}}, {{\\|Socket sTRX4|sTRX4}}, and {{\\|Socket SP3|SP3}} respectively.

Socket sWRX8 is mechanically identical to Socket SP3 and the sockets TR4 and sTRX4 also derived from it. Electrically it differs minimally from Socket SP3 as well, in particular sWRX8 processors support {{abbr|UDIMM}}s in addition to {{abbr|RDIMM}}s, however this infrastructure is restricted to single socket systems with a maximum of one DIMM per memory channel. TR4 and sTRX4 processors support only UDIMMs on up to four memory channels, but up to two DIMMs per channel like Socket SP3, and omit four of eight PCIe interfaces present on Socket SP3 and sWRX8.

TR4 and sTRX4 processors are not supported on Socket sWRX8 or vice versa. If SP3 processors are compatible with sWRX8 platforms or vice versa, given suitable memory and firmware, is unclear.

== Overview ==
Socket sWRX8 is a zero insertion force, screw actuated, [[wikipedia:Surface-mount technology|surface-mount]] [[land grid array]] socket for use with a 4094-contact, 1.00&nbsp;mm × 0.87&nbsp;mm interstitial pitch, organic land grid array CPU package.

This single socket client infrastructure supports eight channels of 72-bit [[DDR4]] memory with a maximum of one DIMM per channel, either {{abbr|UDIMM}}s or {{abbr|RDIMM}}s, eight 16-lane PCIe Gen 4 I/O links, four USB 3.2 Gen 2 ports, and up to 32 SATA Gen 3 ports. Due to the large number of high speed signals 12-layer motherboards are required, 14 layers recommended. 

The following AMD processor families use Socket sWRX8:
{| class="wikitable"
! || CPU Family || Microarch. || Process || Products
|-
|Type 1
|{{amd|CPUID#Family 23 (17h)|Family 17h}} Models 30h–3Fh
|{{amd|Zen 2|l=arch}}
|[[7&nbsp;nm]] & [[12&nbsp;nm]]<!--https://www.amd.com/en/product/9111-->
|Ryzen Threadripper 3900 "{{amd|Castle Peak|l=core}}" (Model 31h)
|-
|Type 2
|{{amd|CPUID#Family 25 (19h)|Family 19h}} Models 00h–0Fh
|{{amd|Zen 3|l=arch}}
|[[7&nbsp;nm]] & [[12&nbsp;nm]](?)
|Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}" (Model 08h)
|}

Codenames of AMD sWRX8 reference platforms ({{abbr|CRB}}s) are "Cloudripper" and "Cloudripper {{abbr|DAP}}".

== Package Description ==
The sWRX8 CPU package is lidded, has a 58.50&nbsp;mm × 75.40&nbsp;mm organic substrate with [[flip chip]] die attachment, and 4094 nickel and gold plated land pads. It ships with a carrier frame pre-installed. The carrier frame, made from an orange colored polycarbonate material, is a part of the package loading mechanism and remains on the package in the socket.

The package substrate has six keying notches along the short edges preventing it from being inserted 180 degrees rotated into the carrier frame or socket, or in an incompatible socket with mismatching keying features. Four additional positions are reserved for future models. However all sockets SP3, TR4, sTRX4, and sWRX8, and all processors for these sockets have the same keying. It is worth noting that these processors are also electrically keyed by pin {{\\|Socket SP3#SP3R1|SP3R1 and SP3R2}}. To boot the processor the motherboard must also provide compatible firmware. A triangular symbol on both sides of the substrate marks the location of pin A1, with corresponding markings on the socket. [[wikipedia:Decoupling capacitor|Decoupling capacitors]] are placed under the lid around the chiplets on the top side, and in two windows in the pad grid on the bottom side.

sWRX8 is a [[multi-chip package]] integrating one central I/O die and 4, 6, or 8 identical Core Complex Dies which contain eight CPU cores each. This silicon is "Starship" rev. SSP-B0 ({{amd|CPUID#Family 23 (17h)|CPU Family 17h}})<!--AMD-56323-0.78 RG 17h 30-3Fh--> and "Genesis" GN-B1 ({{amd|CPUID#Family 25 (19h)|19h}}).<!--AMD-56683-1.04 RG 19h 00-0Fh--> AMD used the same chips for second and third generation EPYC server and embedded processors, and Ryzen Threadripper {{abbr|HEDT}} processors.

sWRX8 has the same memory and I/O interfaces, and the same on-package routing of signals as {{\\|Socket SP3}} {{amd|Socket SP3#Package Description|Type-1/2 packages|l=pack}}, with the differences noted above. The {{abbr|xGMI}} protocol and the {{abbr|WAFL}} interface, used to link processors on dual-socket platforms, are not supported on this socket. If sWRX8 processors are in fact EPYC 7002/7003 processors with different firmware and branding is unclear.

== Socket Description ==
Socket sWRX8 is mechanically identical to {{\\|Socket SP3#Socket Description|Socket SP3}}.

== Features ==
* Lidded [[land grid array]] package, 75.40&nbsp;mm × 58.50&nbsp;mm
** 4094 contacts in a 82 × 55 grid with 0.87&nbsp;mm × 1.00&nbsp;mm interstitial pitch
** Organic substrate, [[flip chip]] die attachment

* 8 × 64/72 bit DDR4 SDRAM interface
** Up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s total raw bandwidth
** One DIMM per channel, up to 8 DIMMs total
** {{abbr|SR}}/{{abbr|DR}} {{abbr|UDIMM}}, {{abbr|RDIMM}}, {{abbr|LRDIMM}}, or {{abbr|3DS RDIMM}} types
** ECC supported
** Memory addressing up to 1&nbsp;TiB/channel<!--AMD-56443-->
** Max. total memory capacity 2&nbsp;TiB using eight 256&nbsp;GiB LRDIMMs or 3DS DIMMs

* Eight multi-function I/O interfaces P0-P3, G0-G3
:{| class="wikitable" style="text-align:center"
|Lane||15||14||13||12||11||10||9||8||7||6||5||4||3||2||1||0
|-
|rowspan="5"|PCIe||colspan="16"|x16
|-
|colspan="8"|x8||colspan="8"|x8
|-
|colspan="4"|x4||colspan="4"|x4||colspan="4"|x4||colspan="4"|x4
|-
|colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2
|-
|x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1
|-
|SATA||colspan="8"| ||7||6||5||4||3||2||1||0
|-
| ||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="4"|PHY 1||colspan="4"|PHY 0
|}
:* PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s) protocol supported on all interfaces
:** 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
:** Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
:** Max. 7 PCIe ports per interface if any lane is configured as SATA port
:** Different PCIe generations supported on the ports in the same interface
:** Lane polarity inversion, per port lane reversal
:** Up to 120 PCIe lanes total (one x8 link reserved for chipset attachment)

:* SATA Gen 1, 2, 3 (6&nbsp;Gb/s) protocol supported on the lower 8 lanes of P0, P1, G2, G3
:** P0: SATA00-07, P1: SATA10-17, G2: SATA20-27, G3: SATA30-37
:** Up to 32 SATA ports total

:* Four {{abbr|PHY}} groups on each interface
:** Lanes sharing a PHY group must use the same protocol (PCIe, SATA)

* 4 × USB 1.1, 2.0, 3.2 Gen 2×1 (10&nbsp;Gb/s) ports
** Type-C connectors are supported with external components

* Low speed interfaces (some sharing pins):
** 2 × 4-wire or 4 × 2-wire {{abbr|UART}} modeled after the [[wikipedia:16550 UART|16550]]
** {{abbr|LPC}}
** 1/2/4-bit {{abbr|SPI/eSPI}} up to 100&nbsp;MHz (SPI) and 66&nbsp;MHz (eSPI)
** 6 × {{abbr|I<sup>2</sup>C}}
** 2 × {{abbr|SMBus}}
** 4 × {{abbr|SGPIO}}
** 2 × SATA {{abbr|DevSlp}}
** 78 × {{abbr|GPIO}}
** Sideband Interface ({{abbr|SB-TSI}})
** 2 × Serial VID Interface (SVI2)
** {{abbr|JTAG}}

== Chipsets ==
sWRX8 processors are {{abbr|SoC}}s with an integrated controller hub so they do not require a chipset, but are paired with the AMD {{amd|WRX80}} chipset (AMD 500-Series)<!--AMD-56437, AMD-56731--> serving as I/O expander.

The chipset is attached with an x8 PCIe link and can provide the following additional interfaces:
* 16 lanes (+ 8-lane CPU link) PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s)
* 8 × SATA Gen 1, 2, 3 (6&nbsp;Gb/s) ports sharing pins with the PCIe interface
* 4 × SATA Gen 1, 2, 3 (6&nbsp;Gb/s) ports, dedicated
* 8 × USB 1.1, 2.0, 3.2 Gen 2 (10&nbsp;Gb/s) ports
* 5 × USB 1.1, 2.0 ports 

An audio interface is not provided by Socket sWRX8 or the chipset, an audio controller is commonly attached as on-board USB device. The sWRX8/WRX80 platform does not support overclocking.

== Processors using Socket sWRX8 ==
<!-- NOTE:
This table is generated automatically from the data in the actual articles.
If a microprocessor is missing from the list, an appropriate article for it needs to be
created and tagged accordingly.
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Launched|Price|{{abbr|OPN}}}}
{{#ask: [[Category:microprocessor models by amd]] [[socket::~*sWRX8]]
|?full page name
|?model number
|?microprocessor family
|?microarchitecture
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency#GHz
|?supported memory type
|?tdp
|?first launched
|?release price
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=15
|mainlabel=-
|valuesep=,<br/>
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[socket::~*sWRX8]]}}
</table>
{{comp table end}}

== Photos ==
{{empty section}}

== Package Diagram ==
[[File:LGA-4094 diag.svg]]

sWRX8 package (same as {{\\|Socket SP3}} package). All dimensions in millimeters.

== Socket Diagrams ==

== Pin Map ==
[[File:Socket SP3 pinmap.svg|800px]]

Socket sWRX8 pinout (same as {{\\|Socket SP3}}, with some {{\\|Socket SP3#Pin Description|constraints}}), top view. This is a preview, click for a larger image and other views.

=== Pin Description ===
See {{\\|Socket SP3#Pin Description|Socket SP3}}.

== Bibliography ==
* {{cite techdoc|title=Socket SP3 Design Specification|publ=AMD|pid=55260|rev=1.16|date=2020-08}}
* {{cite techdoc|title=Functional Data Sheet for sTRX4 and sWRX8 Processors|publ=AMD|pid=56515|rev=0.81|date=2019-08}}
* {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}

== See also ==
* {{\\|Socket AM4}}
* {{\\|Socket TR4}}
* {{\\|Socket sTRX4}}
* {{\\|Socket SP3}}

[[Category:amd]]
designer	AMD +
first launched	July 14, 2020 +
instance of	package +
market segment	Workstation +
microarchitecture	Zen 2 + and Zen 3 +
name	Socket sWRX8 +
package	sWRX8 + and FCLGA-4094 +
package contacts	4,094 +
package height	6.26 mm (0.246 in) +
package length	75.4 mm (7.54 cm, 2.969 in) +
package pitch	0.87 mm (0.0343 in) + and 1 mm (0.0394 in) +
package type	FC-OLGA +
package width	58.5 mm (5.85 cm, 2.303 in) +
socket	sWRX8 +
tdp	280 W (280,000 mW, 0.375 hp, 0.28 kW) +