Editing amd/epyc/7f52

{{amd title|EPYC 7F52}}
{{chip
|name=EPYC 7F52
|no image=Yes
|designer=AMD
|manufacturer=TSMC
|manufacturer 2=GlobalFoundries
|model number=7F52
|market=Server
|first announced=April 14, 2020
|first launched=April 14, 2020
|family=EPYC
|series=7002
|locked=Yes
|frequency=3,500 MHz
|turbo frequency=3,900 MHz
|clock multiplier=35
|isa=x86-64
|isa family=x86
|microarch=Zen 2
|core name=Rome
|core family=23
|process=7 nm
|process 2=14 nm
|technology=CMOS
|mcp=Yes
|die count=9
|word size=64 bit
|core count=16
|thread count=32
|max cpus=2
|max memory=4 TiB
|tdp=240 W
|package name 1=amd,socket_sp3
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7F52 - AMD#pcie +
base frequency	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
clock multiplier	35 +
core count	16 +
core family	23 +
core name	Rome +
designer	AMD +
die count	9 +
family	EPYC +
first announced	April 14, 2020 +
first launched	April 14, 2020 +
full page name	amd/epyc/7f52 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description	8-way set associative +
l1d$ size	512 KiB (524,288 B, 0.5 MiB) +
l1i$ description	8-way set associative +
l1i$ size	512 KiB (524,288 B, 0.5 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ size	256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
ldate	April 14, 2020 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7F52 +
name	EPYC 7F52 +
package	FCLGA-4094 + and SP3 +
part number	100-000000140 + and 100-000000140WOF +
part of	Frequency-optimized SKUs +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 3,100.00 (€ 2,790.00, £ 2,511.00, ¥ 320,323.00) +
release price (tray)	$ 3,100.00 (€ 2,790.00, £ 2,511.00, ¥ 320,323.00) +
series	7002 +
smp max ways	2 +
socket	LGA-4094 + and SP3 +
supported memory type	DDR4-3200 +
tdp	240 W (240,000 mW, 0.322 hp, 0.24 kW) +
technology	CMOS +
thread count	32 +
turbo frequency	3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +