Editing cea-leti/microarchitectures/tsarlet

{{cealeti title|TSARLET|arch}}
{{microarchitecture
|atype=CPU
|name=TSARLET
|designer=CEA-Leti
|manufacturer=STMicroelectronics
|process=28 nm
|process 2=65 nm
|cores=96
|type=Scalar
|type 2=Single-issue
|oooe=No
|speculative=No
|renaming=No
|stages=5
|decode=1-way
|isa=MIPS32v1
|l1i=16 KiB
|l1i per=core
|l1d=16 KiB
|l1d per=core
|l2=256 KiB
|l2 per=core
|l3=1 MiB
|l3 per=core
}}
'''TSARLET''' was a research microarchitecture designed by [[CEA-Leti]] demonstarting the theoretical capabilities of a large-scale high-performance 3D stacked [[chiplets]]-based SoC technology. The project comprised 96 [[MIPS]] cores built using 6 [[chiplets]] [[3D stack]] on an active interposer in order to demonstarte in-package silicon [[scale-out]] capabilities with superior inter-chip capabilities while reducing the overall power and production cost.

== Architecture ==
=== Memory Hierarchy ===
{{empty section}}

== Overview ==
{{empty section}}

== Die ==
=== Compute chiplet ===
* [[STMicroelectronics]] [[28 nm]] [[FDSOI]]
** 10 metal layers
* 4 mm x 5.6 mm (22 mm²) silicon area
* 395,000,000 transistors
* I/O
** 2D
*** 249 signal, 237 power
*** C4 bumps, 200 µm pitch
** 3D
*** 2618 signal
*** up to metal 10 @ 20 µm pitch


:[[File:tsarlet compute chiplet.png|600px]]

=== Base interposer die ===
codename	TSARLET +
core count	96 +
designer	CEA-Leti +
full page name	cea-leti/microarchitectures/tsarlet +
instance of	microarchitecture +
instruction set architecture	MIPS32v1 +
manufacturer	STMicroelectronics +
microarchitecture type	CPU +
name	TSARLET +
pipeline stages	5 +
process	28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) +