Editing cea-leti/microarchitectures/tsarlet

{{cealeti title|96-core 6-chiplet 3D stacked MIPS processor|arch}}
{{microarchitecture}}
'''96-Core 6-Chiplet 3D stacked MIPS processor''' (''no actual name was given to the project'') was a large-scale high-performance SoC technology demonstration by [[CEA-Leti]]. The project comprised 96 [[MIPS]] cores built using 6 [[chiplets]] [[3D stack]] on an active interposer in order to demonstarte in-package silicon [[scale-out]] capabilities with superior inter-chip capabilities while reducing the overall power and production cost.
codename	TSARLET +
core count	96 +
designer	CEA-Leti +
full page name	cea-leti/microarchitectures/tsarlet +
instance of	microarchitecture +
instruction set architecture	MIPS32v1 +
manufacturer	STMicroelectronics +
microarchitecture type	CPU +
name	TSARLET +
pipeline stages	5 +
process	28 nm (0.028 μm, 2.8e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) +